From 0abf2303ac89dd0d0ad88bd7f0bc0a45ffc04ff1 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 24 Nov 2022 19:40:45 +0000
Subject: It runs on the ButterStick

---
 Makefile    | 28 ++++++++++++++++++----------
 example.pcf | 47 ++++++++++++++++++++++++++++++++++++++---------
 example.v   | 21 ++++++++++++++++++---
 firmware.c  |  9 +++------
 4 files changed, 77 insertions(+), 28 deletions(-)

diff --git a/Makefile b/Makefile
index 7672b41..0b7c577 100644
--- a/Makefile
+++ b/Makefile
@@ -1,11 +1,15 @@
-TOOLCHAIN_PREFIX = riscv32-unknown-elf-
+TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf-
 
-ICE40_SIM_CELLS=$(shell yosys-config --datdir/ice40/cells_sim.v)
+ICE40_SIM_CELLS=$(shell yosys-config --datdir/ecp5/cells_sim.v)
+COPY=cp
 
 # set to 4 for simulation
 FIRMWARE_COUNTER_BITS=18
 
-all: example.bin
+all: example.dfu
+
+dfu: example.dfu
+	dfu-util --alt 0 --download $< --reset
 
 ## -------------------
 ## firmware generation
@@ -23,19 +27,23 @@ firmware.bin: firmware.elf
 	chmod -x $@
 
 firmware.hex: firmware.bin
-	python3 ../../firmware/makehex.py $< 128 > $@
+	python3 picorv32/firmware/makehex.py $< 128 > $@
 
 ## ------------------------------
 ## main flow: synth/p&r/bitstream
 
-synth.json: example.v ../../picorv32.v firmware.hex
-	yosys -v3 -l synth.log -p 'synth_ice40 -top top -json $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
+synth.json: example.v picorv32/picorv32.v firmware.hex
+	yosys -v3 -l synth.log -p 'synth_ecp5 -top top -json $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
+
+example_out.config: synth.json example.pcf
+	nextpnr-ecp5 --json $< --textcfg $@ --um5g-85k --speed 8 --package CABGA381 --lpf example.pcf
 
-example.asc: synth.json example.pcf
-	nextpnr-ice40 --hx8k --package ct256 --json $< --pcf example.pcf --asc $@
+example.bit: example_out.config
+	ecppack --compress --freq 38.8 --input $< --bit $@
 
-example.bin: example.asc
-	icepack $< $@
+%.dfu : %.bit
+	$(COPY) $< $@
+	dfu-suffix -v 1209 -p 5af1 -a $@
 
 ## -----------------
 ## icarus simulation
diff --git a/example.pcf b/example.pcf
index a5c7398..6d6ff81 100644
--- a/example.pcf
+++ b/example.pcf
@@ -1,9 +1,38 @@
-set_io clk J3
-set_io LED0 B5
-set_io LED1 B4
-set_io LED2 A2
-set_io LED3 A1
-set_io LED4 C5
-set_io LED5 C4
-set_io LED6 B3
-set_io LED7 C3
+# This is a partial constraints file for ButterStick r1.0,
+# produced based on
+# https://github.com/butterstick-fpga/butterstick-bootloader/blob/main/gateware/rtl/platform/butterstick_r1d0.py
+# All mistakes mine, Tommy Thorn, 2021
+
+LOCATE COMP "clk" SITE "B12";
+IOBUF PORT "clk" IO_TYPE=LVCMOS18;
+FREQUENCY PORT "clk" 30.0 MHz;
+
+LOCATE COMP "rst_n" SITE "R3";
+IOBUF PORT "rst_n" IO_TYPE=LVCMOS33 OPENDRAIN=ON;
+
+LOCATE COMP "user_btn[0]" SITE "U16";
+IOBUF PORT "user_btn[0]" IO_TYPE=SSTL135_I;
+
+LOCATE COMP "user_btn[1]" SITE "T17";
+IOBUF PORT "user_btn[1]" IO_TYPE=SSTL135_I;
+
+LOCATE COMP "LED0" SITE "C13";
+IOBUF PORT "LED0" IO_TYPE=LVCMOS33;
+LOCATE COMP "LED1" SITE "D12";
+IOBUF PORT "LED1" IO_TYPE=LVCMOS33;
+LOCATE COMP "LED2" SITE "U2";
+IOBUF PORT "LED2" IO_TYPE=LVCMOS33;
+LOCATE COMP "LED3" SITE "T3";
+IOBUF PORT "LED3" IO_TYPE=LVCMOS33;
+LOCATE COMP "LED4" SITE "D13";
+IOBUF PORT "LED4" IO_TYPE=LVCMOS33;
+LOCATE COMP "LED5" SITE "E13";
+IOBUF PORT "LED5" IO_TYPE=LVCMOS33;
+LOCATE COMP "LED6" SITE "C16";
+IOBUF PORT "LED6" IO_TYPE=LVCMOS33;
+LOCATE COMP "colour[0]" SITE "T1";
+IOBUF PORT "colour[0]" IO_TYPE=LVCMOS33;
+LOCATE COMP "colour[1]" SITE "R1";
+IOBUF PORT "colour[1]" IO_TYPE=LVCMOS33;
+LOCATE COMP "colour[2]" SITE "U1";
+IOBUF PORT "colour[2]" IO_TYPE=LVCMOS33;
\ No newline at end of file
diff --git a/example.v b/example.v
index e1c64b4..391115b 100644
--- a/example.v
+++ b/example.v
@@ -1,8 +1,9 @@
 `timescale 1 ns / 1 ps
 
 module top (
-	input clk,
-	output reg LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7
+	input            clk,
+	output reg       LED0, LED1, LED2, LED3, LED4, LED5, LED6,
+    output reg [2:0] colour
 );
 	// -------------------------------
 	// Reset Generator
@@ -71,10 +72,24 @@ module top (
 					mem_ready <= 1;
 				end
 				|mem_wstrb && mem_addr == 32'h1000_0000: begin
-					{LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0} <= mem_wdata;
+					{LED6, LED5, LED4, LED3, LED2, LED1, LED0} <= mem_wdata;
 					mem_ready <= 1;
 				end
 			endcase
 		end
 	end
+
+   //always @(posedge clk) begin
+   //   LED0 <= 0;
+   //   LED1 <= 1;
+   //   LED2 <= 0;
+   //   LED3 <= 1;
+   //   LED4 <= 0;
+   //   LED5 <= 1;
+   //   LED6 <= 0;
+   //
+   //   colour[0] <= 1;
+   //   colour[2] <= 1;
+   //end
+   
 endmodule
diff --git a/firmware.c b/firmware.c
index 80a4661..c39ebbd 100644
--- a/firmware.c
+++ b/firmware.c
@@ -45,14 +45,11 @@ void gray(uint8_t c)
 	if (gray_simple != gray_bitwise || gray_decoded != c)
 		while (1) asm volatile ("ebreak");
 
-	output(gray_simple);
+	output(101);
 }
 
 void main()
 {
-	for (uint32_t counter = (2+4+32+64) << SHIFT_COUNTER_BITS;; counter++) {
-		asm volatile ("" : : "r"(counter));
-		if ((counter & ~(~0 << SHIFT_COUNTER_BITS)) == 0)
-			gray(counter >> SHIFT_COUNTER_BITS);
-	}
+	while (1)
+      output(0xAA);
 }
-- 
cgit