From 576d65e2570d114c2e25ac2e25de29d3889af06f Mon Sep 17 00:00:00 2001 From: Xavier Leroy Date: Fri, 18 Aug 2017 11:16:51 +0200 Subject: Update Changelog in preparation for release 3.1 --- Changelog | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'Changelog') diff --git a/Changelog b/Changelog index a8cb6d22..64bcda97 100644 --- a/Changelog +++ b/Changelog @@ -1,3 +1,6 @@ +Release 3.1, 2017-08-18 +======================= + Major improvements: - New port targeting the RISC-V architecture, in 32- and 64-bit modes. @@ -12,6 +15,7 @@ Code generation and optimization: (Avoid reloading the return address from the stack.) - Avoid generating useless conditional branches for empty if/else statements. - Earlier elimination of redundant `&*expr` and `*&expr` addressings. +- Improve utilization of addressing modes for volatile loads and stores. Usability: @@ -31,12 +35,14 @@ Bug fixing: switch cases. - Issue #P16: illegal PowerPC asm generated for unsigned division after constant propagation. -- Issue #P18: ARM PC-relative addressing of constant pool overflows - owing to underestimation of code size. +- Issue #P18: ARM addressing overflows caused by 1- underestimation of + code size, causing mismanagement of constant pool, and 2- large stack + frames where return address and back link are at offsets >= 4Kb. - Pass -no-pie flag to the x86 linker when -pie is the default. Coq and Caml development: +- Support Coq 8.6.1. - Improve compatibility with Coq working version. - Always generate .merlin and _CoqProject files. -- cgit