From 4aa289a5066ebe3081f66c9c0a02fd873720c8ad Mon Sep 17 00:00:00 2001 From: Léo Gourdin Date: Fri, 13 Nov 2020 12:10:46 +0100 Subject: Loads and stores op --- aarch64/PostpassSchedulingOracle.ml | 61 +++++++++++++++++++++---------------- 1 file changed, 35 insertions(+), 26 deletions(-) (limited to 'aarch64/PostpassSchedulingOracle.ml') diff --git a/aarch64/PostpassSchedulingOracle.ml b/aarch64/PostpassSchedulingOracle.ml index 7c8bd144..79a95df9 100644 --- a/aarch64/PostpassSchedulingOracle.ml +++ b/aarch64/PostpassSchedulingOracle.ml @@ -207,18 +207,19 @@ let reg_of_dreg r = Reg (Asm.DR r) let reg_of_ireg r = Reg (Asm.DR (Asm.IR (Asm.RR1 r))) +let reg_of_iregsp r = Reg (Asm.DR (Asm.IR r)) + let reg_of_ireg0 r = match r with Asm.RR0 ir -> reg_of_ireg ir | Asm.XZR -> IREG0_XZR let reg_of_freg r = Reg (Asm.DR (Asm.FR r)) +let reg_of_cr r = Reg (Asm.CR r) + +let regXSP = Reg (Asm.DR (Asm.IR Asm.XSP)) + let flags_wlocs = - [ - Reg (Asm.CR Asm.CN); - Reg (Asm.CR Asm.CZ); - Reg (Asm.CR Asm.CC); - Reg (Asm.CR Asm.CV); - ] + [ reg_of_cr Asm.CN; reg_of_cr Asm.CZ; reg_of_cr Asm.CC; reg_of_cr Asm.CV ] let arith_p_rec i rd = { @@ -296,11 +297,21 @@ let arith_comparison_p_rec i r1 = is_control = false; } +let get_eval_addressing_rlocs a = + match a with + | Asm.ADimm (base, _) -> [ reg_of_iregsp base ] + | Asm.ADreg (base, r) -> [ reg_of_iregsp base; reg_of_ireg r ] + | Asm.ADlsl (base, r, _) -> [ reg_of_iregsp base; reg_of_ireg r ] + | Asm.ADsxt (base, r, _) -> [ reg_of_iregsp base; reg_of_ireg r ] + | Asm.ADuxt (base, r, _) -> [ reg_of_iregsp base; reg_of_ireg r ] + | Asm.ADadr (base, _, _) -> [ reg_of_iregsp base ] + | Asm.ADpostincr (base, _) -> [] + let load_rec ld rd a = { inst = load_rd_a_real ld; write_locs = [ rd ]; - read_locs = [ Mem ]; + read_locs = [ Mem ] @ get_eval_addressing_rlocs a; is_control = false; } @@ -308,7 +319,7 @@ let store_rec st r a = { inst = store_rs_a_real st; write_locs = [ Mem ]; - read_locs = [ r ]; + read_locs = [ r; Mem ] @ get_eval_addressing_rlocs a; is_control = false; } @@ -341,20 +352,18 @@ let cvtx2w_rec rd = let get_testcond_rlocs c = match c with - | Asm.TCeq -> [ Reg (Asm.CR Asm.CZ) ] - | Asm.TCne -> [ Reg (Asm.CR Asm.CZ) ] - | Asm.TChs -> [ Reg (Asm.CR Asm.CC) ] - | Asm.TClo -> [ Reg (Asm.CR Asm.CC) ] - | Asm.TCmi -> [ Reg (Asm.CR Asm.CN) ] - | Asm.TCpl -> [ Reg (Asm.CR Asm.CN) ] - | Asm.TChi -> [ Reg (Asm.CR Asm.CZ); Reg (Asm.CR Asm.CC) ] - | Asm.TCls -> [ Reg (Asm.CR Asm.CZ); Reg (Asm.CR Asm.CC) ] - | Asm.TCge -> [ Reg (Asm.CR Asm.CN); Reg (Asm.CR Asm.CV) ] - | Asm.TClt -> [ Reg (Asm.CR Asm.CN); Reg (Asm.CR Asm.CV) ] - | Asm.TCgt -> - [ Reg (Asm.CR Asm.CN); Reg (Asm.CR Asm.CZ); Reg (Asm.CR Asm.CV) ] - | Asm.TCle -> - [ Reg (Asm.CR Asm.CN); Reg (Asm.CR Asm.CZ); Reg (Asm.CR Asm.CV) ] + | Asm.TCeq -> [ reg_of_cr Asm.CZ ] + | Asm.TCne -> [ reg_of_cr Asm.CZ ] + | Asm.TChs -> [ reg_of_cr Asm.CC ] + | Asm.TClo -> [ reg_of_cr Asm.CC ] + | Asm.TCmi -> [ reg_of_cr Asm.CN ] + | Asm.TCpl -> [ reg_of_cr Asm.CN ] + | Asm.TChi -> [ reg_of_cr Asm.CZ; reg_of_cr Asm.CC ] + | Asm.TCls -> [ reg_of_cr Asm.CZ; reg_of_cr Asm.CC ] + | Asm.TCge -> [ reg_of_cr Asm.CN; reg_of_cr Asm.CV ] + | Asm.TClt -> [ reg_of_cr Asm.CN; reg_of_cr Asm.CV ] + | Asm.TCgt -> [ reg_of_cr Asm.CN; reg_of_cr Asm.CZ; reg_of_cr Asm.CV ] + | Asm.TCle -> [ reg_of_cr Asm.CN; reg_of_cr Asm.CZ; reg_of_cr Asm.CV ] let cset_rec rd c = { @@ -395,19 +404,19 @@ let allocframe_rec sz linkofs = write_locs = [ Mem; - Reg (Asm.DR (Asm.IR Asm.XSP)); + regXSP; reg_of_ireg Asm.X16; reg_of_ireg Asm.X29; ]; - read_locs = [ Reg (Asm.DR (Asm.IR Asm.XSP)) ]; + read_locs = [ regXSP ]; is_control = false; } let freeframe_rec sz linkofs = { inst = freeframe_real; - write_locs = [ Mem; Reg (Asm.DR (Asm.IR Asm.XSP)); reg_of_ireg Asm.X16 ]; - read_locs = [ Mem; Reg (Asm.DR (Asm.IR Asm.XSP)) ]; + write_locs = [ Mem; regXSP; reg_of_ireg Asm.X16 ]; + read_locs = [ Mem; regXSP ]; is_control = false; } -- cgit