From 29e0c9b2c99a437fc9dfab66e1abdd546a5308d6 Mon Sep 17 00:00:00 2001 From: xleroy Date: Thu, 2 Jan 2014 15:59:11 +0000 Subject: Updated ARM backend wrt new static analyses and optimizations. NeedOp, Deadcode: must have distinct needs per argument of an operator. This change remains to be propagated to IA32 and PPC. git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2399 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e --- arm/Asmgenproof1.v | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arm/Asmgenproof1.v') diff --git a/arm/Asmgenproof1.v b/arm/Asmgenproof1.v index 21d2b73c..1e65d72e 100644 --- a/arm/Asmgenproof1.v +++ b/arm/Asmgenproof1.v @@ -917,6 +917,26 @@ Proof. generalize (addimm_correct x IR13 i k rs m). intros [rs' [EX [RES OTH]]]. exists rs'; auto with asmgen. + (* Ocast8signed *) + set (rs1 := nextinstr (rs#x <- (Val.shl rs#x0 (Vint (Int.repr 24))))). + set (rs2 := nextinstr (rs1#x <- (Val.shr rs1#x (Vint (Int.repr 24))))). + exists rs2. + split. apply exec_straight_two with rs1 m; auto. + split. unfold rs2; Simpl. unfold rs1; Simpl. + unfold Val.shr, Val.shl; destruct (rs x0); auto. + change (Int.ltu (Int.repr 24) Int.iwordsize) with true; simpl. + f_equal. symmetry. apply (Int.sign_ext_shr_shl 8). compute; auto. + intros. unfold rs2, rs1; Simpl. + (* Ocast16signed *) + set (rs1 := nextinstr (rs#x <- (Val.shl rs#x0 (Vint (Int.repr 16))))). + set (rs2 := nextinstr (rs1#x <- (Val.shr rs1#x (Vint (Int.repr 16))))). + exists rs2. + split. apply exec_straight_two with rs1 m; auto. + split. unfold rs2; Simpl. unfold rs1; Simpl. + unfold Val.shr, Val.shl; destruct (rs x0); auto. + change (Int.ltu (Int.repr 16) Int.iwordsize) with true; simpl. + f_equal. symmetry. apply (Int.sign_ext_shr_shl 16). compute; auto. + intros. unfold rs2, rs1; Simpl. (* Oaddimm *) generalize (addimm_correct x x0 i k rs m). intros [rs' [A [B C]]]. -- cgit