From 362f2f36a44fa6ab4fe28264ed572d721adece70 Mon Sep 17 00:00:00 2001 From: xleroy Date: Fri, 3 Jan 2014 17:09:54 +0000 Subject: Introduce and use the platform-specific Archi module giving: - endianness - alignment constraints for 8-byte types (which is 4 for x86 ABI and 8 for other ABIs) - NaN handling options (superceding the Nan module, removed). git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2402 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e --- backend/Regalloc.ml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'backend/Regalloc.ml') diff --git a/backend/Regalloc.ml b/backend/Regalloc.ml index 5c68602c..b21eeb0a 100644 --- a/backend/Regalloc.ml +++ b/backend/Regalloc.ml @@ -150,9 +150,9 @@ let block_of_RTL_instr funsig tyenv = function | None -> assert false | Some addr' -> [Xload(Mint32, addr, vregs tyenv args, - V((if big_endian then dst else twin_reg dst), Tint)); + V((if Archi.big_endian then dst else twin_reg dst), Tint)); Xload(Mint32, addr', vregs tyenv args, - V((if big_endian then twin_reg dst else dst), Tint)); + V((if Archi.big_endian then twin_reg dst else dst), Tint)); Xbranch s] end else [Xload(chunk, addr, vregs tyenv args, vreg tyenv dst); Xbranch s] @@ -162,9 +162,9 @@ let block_of_RTL_instr funsig tyenv = function | None -> assert false | Some addr' -> [Xstore(Mint32, addr, vregs tyenv args, - V((if big_endian then src else twin_reg src), Tint)); + V((if Archi.big_endian then src else twin_reg src), Tint)); Xstore(Mint32, addr', vregs tyenv args, - V((if big_endian then twin_reg src else src), Tint)); + V((if Archi.big_endian then twin_reg src else src), Tint)); Xbranch s] end else [Xstore(chunk, addr, vregs tyenv args, vreg tyenv src); Xbranch s] -- cgit