From edc7505f0b1b617cda01648316ea02b58d268411 Mon Sep 17 00:00:00 2001
From: Léo Gourdin This web page is a patched version of the table of contents of the official CompCert sources documentation, as given on the CompCert Web site.
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The people responsible for this version are with contributions of:Commented Coq development
Version 3.9, 2021-05-10
-VERIMAG fork version 2021-29-10
+VERIMAG fork version 2021-29-10
The CompCert Verimag's fork
A high-level view of this CompCert backend is provided by the following documents:
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Pass | Source & target | @@ -301,6 +342,60 @@ code.Unusedglobproof | |||
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Passes introduced for profiling (for later use in trace selection) | +|||||
Insert profiling annotations (for recording experiments -- see PROFILE.md). + | +RTL to RTL | +Profiling | +Profilingproof | +||
Update ICond nodes (from recorded experiments -- see PROFILE.md). + | +RTL to RTL | +ProfilingExploit | +ProfilingExploitproof | +||
Passes introduced for superblock prepass scheduling | +|||||
Code duplications (trace selection, loop unrollings, etc) + | +RTL to RTL | +Duplicate (generic checker) | +Duplicateproof (generic proof) + Duplicatepasses (several passes from several oracles) |
+||
Superblock selection (with Liveness information) | +RTL to RTLPath | +RTLpathLivegen | +RTLpathLivegenproof | +||
Superblock prepass scheduling | +RTLPath to RTLPath | +RTLpathScheduler | +RTLpathSchedulerproof + with RTLpathSE_theory (the theory of symbolic execution on RTLpath) + and RTLpathSE_simu_specs (the low-level specifications of the simulation checker) + and RTLpathSE_impl (the simulation checker with hash-consing) |
+||
Forgeting superblocks | +RTLPath to RTL | +RTLpath.transf_program | +RTLpathproof | +||
Passes from register allocation | +|||||
Register allocation (validation a posteriori) | RTL to LTL | @@ -311,8 +406,8 @@ code.||||
Branch tunneling | LTL to LTL | -Tunneling | -Tunnelingproof | +LTLTunneling | +LTLTunnelingproof |
Emission of assembly code | -Mach to Asm | +||||
Passes introduced for KVX VLIW | +|||||
Reconstruction of basic-blocks at Mach level | +Mach to Machblock | +Machblockgen | +ForwardSimulationBlock + Machblockgenproof |
+||
Emission of purely sequential assembly code | +Machblock to Asmblock | +Asmblockgen | +Asmblockgenproof0 + Asmblockgenproof1 + Asmblockgenproof |
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Bundling (and basic-block scheduling) | +Asmblock to Asmvliw | +PostpassScheduling + using Asmblockdeps + and the abstractbb library |
+ PostpassSchedulingproof | +||
Flattening bundles (only a bureaucratic operation) | +Asmvliw to Asm | Asmgen | -Asmgenproof0 - Asmgenproof1 - Asmgenproof |
+ Asmgenproof (whole simulation proof from Mach to Asm) |