From f642817f0dc761e51c3bd362f75b0068a8d4b0c8 Mon Sep 17 00:00:00 2001 From: Xavier Leroy Date: Fri, 28 Apr 2017 15:56:59 +0200 Subject: RISC-V port and assorted changes This commits adds code generation for the RISC-V architecture, both in 32- and 64-bit modes. The generated code was lightly tested using the simulator and cross-binutils from https://riscv.org/software-tools/ This port required the following additional changes: - Integers: More properties about shrx - SelectOp: now provides smart constructors for mulhs and mulhu - SelectDiv, 32-bit integer division and modulus: implement constant propagation, use the new smart constructors mulhs and mulhu. - Runtime library: if no asm implementation is provided, run the reference C implementation through CompCert. Since CompCert rejects the definitions of names of special functions such as __i64_shl, the reference implementation now uses "i64_" names, e.g. "i64_shl", and a renaming "i64_ -> __i64_" is performed over the generated assembly file, before assembling and building the runtime library. - test/: add SIMU make variable to run tests through a simulator - test/regression/alignas.c: make sure _Alignas and _Alignof are not #define'd by C headers commit da14495c01cf4f66a928c2feff5c53f09bde837f Author: Xavier Leroy Date: Thu Apr 13 17:36:10 2017 +0200 RISC-V port, continued Now working on Asmgen. commit 36f36eb3a5abfbb8805960443d087b6a83e86005 Author: Xavier Leroy Date: Wed Apr 12 17:26:39 2017 +0200 RISC-V port, first steps This port is based on Prashanth Mundkur's experimental RV32 port and brings it up to date with CompCert, and adds 64-bit support (RV64). Work in progress. --- lib/Integers.v | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'lib/Integers.v') diff --git a/lib/Integers.v b/lib/Integers.v index 8fd09dd1..b1fa982d 100644 --- a/lib/Integers.v +++ b/lib/Integers.v @@ -796,6 +796,12 @@ Proof. unfold signed. rewrite unsigned_zero. apply zlt_true. generalize half_modulus_pos; omega. Qed. +Theorem signed_one: zwordsize > 1 -> signed one = 1. +Proof. + intros. unfold signed. rewrite unsigned_one. apply zlt_true. + change 1 with (two_p 0). rewrite half_modulus_power. apply two_p_monotone_strict. omega. +Qed. + Theorem signed_mone: signed mone = -1. Proof. unfold signed. rewrite unsigned_mone. @@ -1844,6 +1850,15 @@ Proof. destruct (testbit x i); destruct (testbit y i); reflexivity || discriminate. Qed. +Theorem xor_is_zero: forall x y, eq (xor x y) zero = eq x y. +Proof. + intros. predSpec eq eq_spec (xor x y) zero. +- apply xor_zero_equal in H. subst y. rewrite eq_true; auto. +- predSpec eq eq_spec x y. ++ elim H; subst y; apply xor_idem. ++ auto. +Qed. + Theorem and_xor_distrib: forall x y z, and x (xor y z) = xor (and x y) (and x z). @@ -2933,6 +2948,13 @@ Proof. - apply Zquot_Zdiv_pos; omega. Qed. +Theorem shrx_zero: + forall x, zwordsize > 1 -> shrx x zero = x. +Proof. + intros. unfold shrx. rewrite shl_zero. unfold divs. rewrite signed_one by auto. + rewrite Z.quot_1_r. apply repr_signed. +Qed. + Theorem shrx_shr: forall x y, ltu y (repr (zwordsize - 1)) = true -> @@ -4080,9 +4102,7 @@ Qed. Theorem shrx'_zero: forall x, shrx' x Int.zero = x. Proof. - intros. unfold shrx'. rewrite shl'_one_two_p. unfold divs. - change (signed (repr (two_p (Int.unsigned Int.zero)))) with 1. - rewrite Z.quot_1_r. apply repr_signed. + intros. change (shrx' x Int.zero) with (shrx x zero). apply shrx_zero. compute; auto. Qed. Theorem shrx'_shr_2: -- cgit