From 225e51bcf9bfe4029e0d9ca5617ad288326e68c9 Mon Sep 17 00:00:00 2001 From: David Monniaux Date: Tue, 2 Feb 2021 15:44:38 +0100 Subject: implement for another register configuration --- riscV/Asmexpand.ml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'riscV') diff --git a/riscV/Asmexpand.ml b/riscV/Asmexpand.ml index f23db36e..1f6597d1 100644 --- a/riscV/Asmexpand.ml +++ b/riscV/Asmexpand.ml @@ -592,7 +592,14 @@ let expand_instruction instr = if not (ireg0_eq rt rf) then if (ireg0_eq (X rd) rt) - then failwith "Pselectl rd=rt" + then + begin + emit (Psubl(X31, X0, rb)); + emit (Pandl(X31, X X31, rt)); + emit (Paddil(rd, rb, Int64.mone)); + emit (Pandl(rd, X rd, rf)); + emit (Porl(rd, X rd, X X31)) + end else if (ireg0_eq (X rd) rf) then -- cgit