From e9f40aaca38ba81f3e9e5c0a5e03de9fa074d838 Mon Sep 17 00:00:00 2001 From: Xavier Leroy Date: Thu, 10 Jun 2021 09:52:47 +0200 Subject: Int.sign_ext_shr_shl: weaker hypothesis Works also for sign_ext 32. ARM, RISC-V: adapt Asmgenproof1 accordingly --- riscV/Asmgenproof1.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'riscV') diff --git a/riscV/Asmgenproof1.v b/riscV/Asmgenproof1.v index 8195ce44..af53754e 100644 --- a/riscV/Asmgenproof1.v +++ b/riscV/Asmgenproof1.v @@ -1010,14 +1010,14 @@ Opaque Int.eq. split; intros; Simpl. assert (A: Int.ltu (Int.repr 24) Int.iwordsize = true) by auto. destruct (rs x0); auto; simpl. rewrite A; simpl. rewrite A. - apply Val.lessdef_same. f_equal. apply Int.sign_ext_shr_shl. split; reflexivity. + apply Val.lessdef_same. f_equal. apply Int.sign_ext_shr_shl. compute; intuition congruence. - (* cast16signed *) econstructor; split. eapply exec_straight_two. simpl;eauto. simpl;eauto. auto. auto. split; intros; Simpl. assert (A: Int.ltu (Int.repr 16) Int.iwordsize = true) by auto. destruct (rs x0); auto; simpl. rewrite A; simpl. rewrite A. - apply Val.lessdef_same. f_equal. apply Int.sign_ext_shr_shl. split; reflexivity. + apply Val.lessdef_same. f_equal. apply Int.sign_ext_shr_shl. compute; intuition congruence. - (* addimm *) exploit (opimm32_correct Paddw Paddiw Val.add); auto. instantiate (1 := x0); eauto with asmgen. intros (rs' & A & B & C). -- cgit From c34d25e011402aedad62b3fe9b7b04989df4522e Mon Sep 17 00:00:00 2001 From: Xavier Leroy Date: Thu, 23 Sep 2021 12:52:11 +0200 Subject: Fix wrong expansion of __builtin_memcpy_aligned In the "small" case, there was an error in the choice of temporary registers to use when one argument is a stack location and the other is a register. The chosen temporary could conflict with the argument that resides in a register. Fixes: #412 --- riscV/Asmexpand.ml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'riscV') diff --git a/riscV/Asmexpand.ml b/riscV/Asmexpand.ml index dc0ec184..ab0e6fee 100644 --- a/riscV/Asmexpand.ml +++ b/riscV/Asmexpand.ml @@ -170,8 +170,8 @@ let memcpy_small_arg sz arg tmp = assert false let expand_builtin_memcpy_small sz al src dst = - let (tsrc, tdst) = - if dst <> BA (IR X5) then (X5, X6) else (X6, X5) in + let tsrc = if dst <> BA (IR X5) then X5 else X6 in + let tdst = if src <> BA (IR X6) then X6 else X5 in let (rsrc, osrc) = memcpy_small_arg sz src tsrc in let (rdst, odst) = memcpy_small_arg sz dst tdst in let rec copy osrc odst sz = -- cgit