From dc4bed2cf06f46687225275131f411c86c773598 Mon Sep 17 00:00:00 2001 From: xleroy Date: Sun, 21 Dec 2008 13:32:24 +0000 Subject: Revised back-end so that only 2 integer registers are reserved for reloading. git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@925 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e --- backend/LTLintyping.v | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'backend/LTLintyping.v') diff --git a/backend/LTLintyping.v b/backend/LTLintyping.v index 1c0c3f30..26ec066d 100644 --- a/backend/LTLintyping.v +++ b/backend/LTLintyping.v @@ -19,6 +19,7 @@ Require Import Op. Require Import RTL. Require Import Locations. Require Import LTLin. +Require LTLtyping. Require Import Conventions. (** The following predicates define a type system for LTLin similar to that @@ -53,17 +54,15 @@ Inductive wt_instr : instruction -> Prop := wt_instr (Lstore chunk addr args src) | wt_Lcall: forall sig ros args res, - match ros with inl r => Loc.type r = Tint | inr s => True end -> List.map Loc.type args = sig.(sig_args) -> - Loc.type res = match sig.(sig_res) with None => Tint | Some ty => ty end -> - match ros with inl r => loc_acceptable r | inr s => True end -> + Loc.type res = proj_sig_res sig -> + LTLtyping.call_loc_acceptable sig ros -> locs_acceptable args -> loc_acceptable res -> wt_instr (Lcall sig ros args res) | wt_Ltailcall: forall sig ros args, - match ros with inl r => Loc.type r = Tint | inr s => True end -> List.map Loc.type args = sig.(sig_args) -> - match ros with inl r => loc_acceptable r | inr s => True end -> + LTLtyping.call_loc_acceptable sig ros -> locs_acceptable args -> sig.(sig_res) = funsig.(sig_res) -> Conventions.tailcall_possible sig -> -- cgit