From ab617cf8e6e60e8de3eb8de220f71dd05c18209f Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 27 Apr 2023 16:32:13 +0100 Subject: Update verilog back end with new x86 changes --- verilog/Asmgen.v | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'verilog/Asmgen.v') diff --git a/verilog/Asmgen.v b/verilog/Asmgen.v index 73e3263e..f8d25a50 100644 --- a/verilog/Asmgen.v +++ b/verilog/Asmgen.v @@ -585,6 +585,12 @@ Definition transl_op | Odivf, a1 :: a2 :: nil => assertion (mreg_eq a1 res); do r <- freg_of res; do r2 <- freg_of a2; OK (Pdivd_ff r r2 :: k) + | Omaxf, a1 :: a2 :: nil => + assertion (mreg_eq a1 res); + do r <- freg_of res; do r2 <- freg_of a2; OK (Pmaxsd r r2 :: k) + | Ominf, a1 :: a2 :: nil => + assertion (mreg_eq a1 res); + do r <- freg_of res; do r2 <- freg_of a2; OK (Pminsd r r2 :: k) | Onegfs, a1 :: nil => assertion (mreg_eq a1 res); do r <- freg_of res; OK (Pnegs r :: k) -- cgit