From 81e3066c13050677c5bc44ddbd22bd7c98f0e3e3 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Mon, 28 Sep 2020 19:29:14 +0100 Subject: Add Verilog backend --- verilog/Machregsaux.ml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 verilog/Machregsaux.ml (limited to 'verilog/Machregsaux.ml') diff --git a/verilog/Machregsaux.ml b/verilog/Machregsaux.ml new file mode 100644 index 00000000..a48749a5 --- /dev/null +++ b/verilog/Machregsaux.ml @@ -0,0 +1,15 @@ +(* *********************************************************************) +(* *) +(* The Compcert verified compiler *) +(* *) +(* Xavier Leroy, INRIA Paris-Rocquencourt *) +(* *) +(* Copyright Institut National de Recherche en Informatique et en *) +(* Automatique. All rights reserved. This file is distributed *) +(* under the terms of the INRIA Non-Commercial License Agreement. *) +(* *) +(* *********************************************************************) + +(** Auxiliary functions on machine registers *) + +let is_scratch_register r = false -- cgit