From 0bea8428f342a455c5ca720cbac02be111da7120 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 15 Dec 2016 12:51:31 +0100
Subject: Suppress iverilog warnings re parameters in "make test_synth"

---
 Makefile    | 2 +-
 testbench.v | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index b1e3c66..4402ae9 100644
--- a/Makefile
+++ b/Makefile
@@ -49,7 +49,7 @@ testbench_sp.vvp: testbench.v picorv32.v
 	chmod -x testbench_sp.vvp
 
 testbench_synth.vvp: testbench.v synth.v
-	iverilog -o testbench_synth.vvp testbench.v synth.v
+	iverilog -o testbench_synth.vvp -DSYNTH_TEST testbench.v synth.v
 	chmod -x testbench_synth.vvp
 
 synth.v: picorv32.v scripts/yosys/synth_sim.ys
diff --git a/testbench.v b/testbench.v
index 18cce40..84a2fd0 100644
--- a/testbench.v
+++ b/testbench.v
@@ -139,6 +139,7 @@ module picorv32_wrapper #(
 	);
 
 	picorv32_axi #(
+`ifndef SYNTH_TEST
 `ifdef SP_TEST
 		.ENABLE_REGS_DUALPORT(0),
 `endif
@@ -149,6 +150,7 @@ module picorv32_wrapper #(
 		.ENABLE_DIV(1),
 		.ENABLE_IRQ(1),
 		.ENABLE_TRACE(1)
+`endif
 	) uut (
 		.clk            (clk            ),
 		.resetn         (resetn         ),
-- 
cgit