From 3f9b5048bc26e3fa1cf7d13504f502d28ee99051 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 22 Sep 2019 13:59:43 +0200 Subject: Fix initialization of "irq" in verilog testbench Signed-off-by: Clifford Wolf --- testbench.v | 2 +- testbench_wb.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench.v b/testbench.v index eee2676..9d8e249 100644 --- a/testbench.v +++ b/testbench.v @@ -75,7 +75,7 @@ module picorv32_wrapper #( output [35:0] trace_data ); wire tests_passed; - reg [31:0] irq; + reg [31:0] irq = 0; reg [15:0] count_cycle = 0; always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0; diff --git a/testbench_wb.v b/testbench_wb.v index e78dbfa..4e1a8eb 100644 --- a/testbench_wb.v +++ b/testbench_wb.v @@ -65,7 +65,7 @@ module picorv32_wrapper #( output [35:0] trace_data ); wire tests_passed; - reg [31:0] irq; + reg [31:0] irq = 0; wire mem_instr; reg [15:0] count_cycle = 0; -- cgit