From 94edf3565dcd4d3cb581216d9a035d047e50c0f6 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 9 Jul 2015 02:48:14 +0200
Subject: Vivado "system" example

---
 scripts/vivado/.gitignore       | 14 +++++++++
 scripts/vivado/Makefile         | 40 +++++++++++++++++++++++--
 scripts/vivado/firmware.S       | 12 ++++++++
 scripts/vivado/firmware.c       | 14 +++++++++
 scripts/vivado/firmware.lds     | 11 +++++++
 scripts/vivado/soc_top.v        | 65 -----------------------------------------
 scripts/vivado/synth_soc.tcl    | 17 -----------
 scripts/vivado/synth_soc.xdc    | 34 ---------------------
 scripts/vivado/synth_system.tcl | 17 +++++++++++
 scripts/vivado/synth_system.xdc | 34 +++++++++++++++++++++
 scripts/vivado/system.v         | 65 +++++++++++++++++++++++++++++++++++++++++
 scripts/vivado/system_tb.v      | 34 +++++++++++++++++++++
 12 files changed, 239 insertions(+), 118 deletions(-)
 create mode 100644 scripts/vivado/firmware.S
 create mode 100644 scripts/vivado/firmware.c
 create mode 100644 scripts/vivado/firmware.lds
 delete mode 100644 scripts/vivado/soc_top.v
 delete mode 100644 scripts/vivado/synth_soc.tcl
 delete mode 100644 scripts/vivado/synth_soc.xdc
 create mode 100644 scripts/vivado/synth_system.tcl
 create mode 100644 scripts/vivado/synth_system.xdc
 create mode 100644 scripts/vivado/system.v
 create mode 100644 scripts/vivado/system_tb.v

diff --git a/scripts/vivado/.gitignore b/scripts/vivado/.gitignore
index bdaae89..2374269 100644
--- a/scripts/vivado/.gitignore
+++ b/scripts/vivado/.gitignore
@@ -1,4 +1,18 @@
+.Xil/
+firmware.bin
+firmware.elf
+firmware.hex
+firmware.map
 synth_*.log
 synth_*.mmi
 synth_*.bit
+synth_system.v
+table.txt
 tab_*/
+webtalk.jou
+webtalk.log
+webtalk_*.jou
+webtalk_*.log
+xelab.*
+xsim.*
+xvlog.*
diff --git a/scripts/vivado/Makefile b/scripts/vivado/Makefile
index f5f6129..3b46bf3 100644
--- a/scripts/vivado/Makefile
+++ b/scripts/vivado/Makefile
@@ -1,8 +1,26 @@
 
-export VIVADO = /opt/Xilinx/Vivado/2015.1/bin/vivado
+VIVADO = /opt/Xilinx/Vivado/2015.1/bin/vivado
+XVLOG = /opt/Xilinx/Vivado/2015.1/bin/xvlog
+XELAB = /opt/Xilinx/Vivado/2015.1/bin/xelab
+GLBL = /opt/Xilinx/Vivado/2015.1/data/verilog/src/glbl.v
+TOOLCHAIN_PREFIX = riscv64-unknown-elf-
+
+export VIVADO
 
 help:
-	@echo "Usage: make {synth_speed|synth_area|synth_soc}"
+	@echo ""
+	@echo "Simple synthesis tests:"
+	@echo "  make synth_area_{small|regular|large}"
+	@echo "  make synth_speed"
+	@echo ""
+	@echo "Example system:"
+	@echo "  make synth_system"
+	@echo "  make sim_system"
+	@echo ""
+	@echo "Timing and Utilization Evaluation:"
+	@echo "  make table.txt"
+	@echo "  make area"
+	@echo ""
 
 synth_%:
 	rm -f $@.log
@@ -11,6 +29,19 @@ synth_%:
 	-grep -B4 -A10 'Slice LUTs' $@.log
 	-grep -B1 -A9 ^Slack $@.log && echo
 
+synth_system: firmware.hex
+
+sim_system:
+	$(XVLOG) system_tb.v synth_system.v
+	$(XVLOG) $(GLBL)
+	$(XELAB) -L unifast_ver -L unisims_ver -R system_tb glbl
+
+firmware.hex: firmware.S firmware.c firmware.lds
+	$(TOOLCHAIN_PREFIX)gcc -Os -m32 -ffreestanding -nostdlib -o firmware.elf firmware.S firmware.c \
+		 -Wl,-Bstatic,-T,firmware.lds,-Map,firmware.map,--strip-debug -lgcc
+	$(TOOLCHAIN_PREFIX)objcopy -O binary firmware.elf firmware.bin
+	python3 ../../firmware/makehex.py firmware.bin > firmware.hex
+
 tab_%/results.txt:
 	bash tabtest.sh $@
 
@@ -24,3 +55,8 @@ table.txt: tab_small_xc7v_1/results.txt tab_small_xc7v_2/results.txt tab_small_x
 table.txt:
 	bash table.sh > table.txt
 
+clean:
+	rm -rf .Xil/ firmware.bin firmware.elf firmware.hex firmware.map synth_*.log
+	rm -rf synth_*.mmi synth_*.bit synth_system.v table.txt tab_*/ webtalk.jou
+	rm -rf webtalk.log webtalk_*.jou webtalk_*.log xelab.* xsim.* xvlog.*
+
diff --git a/scripts/vivado/firmware.S b/scripts/vivado/firmware.S
new file mode 100644
index 0000000..ae554fb
--- /dev/null
+++ b/scripts/vivado/firmware.S
@@ -0,0 +1,12 @@
+.section .init
+.global main
+
+/* set stack pointer */
+lui sp, %hi(16*1024)
+addi sp, sp, %lo(16*1024)
+
+/* call main */
+jal ra, main
+
+/* break */
+sbreak
diff --git a/scripts/vivado/firmware.c b/scripts/vivado/firmware.c
new file mode 100644
index 0000000..95aa8de
--- /dev/null
+++ b/scripts/vivado/firmware.c
@@ -0,0 +1,14 @@
+void putc(char c)
+{
+	*(volatile char*)0x10000000 = c;
+}
+
+void puts(const char *s)
+{
+	while (*s) putc(*s++);
+}
+
+void main()
+{
+	puts("Hello World!\n");
+}
diff --git a/scripts/vivado/firmware.lds b/scripts/vivado/firmware.lds
new file mode 100644
index 0000000..970000a
--- /dev/null
+++ b/scripts/vivado/firmware.lds
@@ -0,0 +1,11 @@
+SECTIONS {
+	.memory : {
+		. = 0x000000;
+		*(.init);
+		*(.text);
+		*(*);
+		. = ALIGN(4);
+		end = .;
+	}
+}
+
diff --git a/scripts/vivado/soc_top.v b/scripts/vivado/soc_top.v
deleted file mode 100644
index b0ebb00..0000000
--- a/scripts/vivado/soc_top.v
+++ /dev/null
@@ -1,65 +0,0 @@
-`timescale 1 ns / 1 ps
-
-module soc_top (
-	input            clk,
-	input            resetn,
-	output           trap,
-	output reg [7:0] out_byte,
-	output reg       out_byte_en
-);
-	// 4096 32bit words = 16kB memory
-	parameter MEM_SIZE = 4096;
-
-	wire mem_valid;
-	wire mem_instr;
-	wire mem_ready;
-	wire [31:0] mem_addr;
-	wire [31:0] mem_wdata;
-	wire [3:0] mem_wstrb;
-	reg [31:0] mem_rdata;
-
-	wire mem_la_read;
-	wire mem_la_write;
-	wire [31:0] mem_la_addr;
-	wire [31:0] mem_la_wdata;
-	wire [3:0] mem_la_wstrb;
-
-	picorv32 uut (
-		.clk         (clk         ),
-		.resetn      (resetn      ),
-		.trap        (trap        ),
-		.mem_valid   (mem_valid   ),
-		.mem_instr   (mem_instr   ),
-		.mem_ready   (mem_ready   ),
-		.mem_addr    (mem_addr    ),
-		.mem_wdata   (mem_wdata   ),
-		.mem_wstrb   (mem_wstrb   ),
-		.mem_rdata   (mem_rdata   ),
-		.mem_la_read (mem_la_read ),
-		.mem_la_write(mem_la_write),
-		.mem_la_addr (mem_la_addr ),
-		.mem_la_wdata(mem_la_wdata),
-		.mem_la_wstrb(mem_la_wstrb)
-	);
-
-	reg [31:0] memory [0:MEM_SIZE-1];
-	// initial $readmemh("firmware.hex", memory);
-
-	assign mem_ready = 1;
-
-	always @(posedge clk) begin
-		out_byte_en <= 0;
-		mem_rdata <= memory[mem_la_addr >> 2];
-		if (mem_la_write && (mem_la_addr >> 2) < MEM_SIZE) begin
-			if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0];
-			if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8];
-			if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16];
-			if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24];
-		end
-		else
-		if (mem_la_write && mem_la_addr == 32'h1000_0000) begin
-			out_byte_en <= 1;
-			out_byte <= mem_la_wdata;
-		end
-	end
-endmodule
diff --git a/scripts/vivado/synth_soc.tcl b/scripts/vivado/synth_soc.tcl
deleted file mode 100644
index eaf82d5..0000000
--- a/scripts/vivado/synth_soc.tcl
+++ /dev/null
@@ -1,17 +0,0 @@
-
-read_verilog soc_top.v
-read_verilog ../../picorv32.v
-read_xdc synth_soc.xdc
-
-synth_design -part xc7a35t-cpg236-1 -top soc_top
-opt_design
-place_design
-route_design
-
-report_utilization
-report_timing
-
-write_verilog -force synth_soc.v
-write_bitstream -force synth_soc.bit
-# write_mem_info -force synth_soc.mmi
-
diff --git a/scripts/vivado/synth_soc.xdc b/scripts/vivado/synth_soc.xdc
deleted file mode 100644
index 5748466..0000000
--- a/scripts/vivado/synth_soc.xdc
+++ /dev/null
@@ -1,34 +0,0 @@
-
-# XDC File for Basys3 Board
-###########################
-
-set_property PACKAGE_PIN W5 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-create_clock -period 10.00 [get_ports clk]
-
-# Pmod Header JA (JA0..JA7)
-set_property PACKAGE_PIN J1 [get_ports {out_byte[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[0]}]
-set_property PACKAGE_PIN L2 [get_ports {out_byte[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[1]}]
-set_property PACKAGE_PIN J2 [get_ports {out_byte[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[2]}]
-set_property PACKAGE_PIN G2 [get_ports {out_byte[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[3]}]
-set_property PACKAGE_PIN H1 [get_ports {out_byte[4]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[4]}]
-set_property PACKAGE_PIN K2 [get_ports {out_byte[5]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[5]}]
-set_property PACKAGE_PIN H2 [get_ports {out_byte[6]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[6]}]
-set_property PACKAGE_PIN G3 [get_ports {out_byte[7]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[7]}]
-
-# Pmod Header JB (JB0..JB2)
-set_property PACKAGE_PIN A14 [get_ports {resetn}]
-set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
-set_property PACKAGE_PIN A16 [get_ports {trap}]
-set_property IOSTANDARD LVCMOS33 [get_ports {trap}]
-set_property PACKAGE_PIN B15 [get_ports {out_byte_en}]
-set_property IOSTANDARD LVCMOS33 [get_ports {out_byte_en}]
-
diff --git a/scripts/vivado/synth_system.tcl b/scripts/vivado/synth_system.tcl
new file mode 100644
index 0000000..26ea01c
--- /dev/null
+++ b/scripts/vivado/synth_system.tcl
@@ -0,0 +1,17 @@
+
+read_verilog system.v
+read_verilog ../../picorv32.v
+read_xdc synth_system.xdc
+
+synth_design -part xc7a35t-cpg236-1 -top system
+opt_design
+place_design
+route_design
+
+report_utilization
+report_timing
+
+write_verilog -force synth_system.v
+write_bitstream -force synth_system.bit
+# write_mem_info -force synth_system.mmi
+
diff --git a/scripts/vivado/synth_system.xdc b/scripts/vivado/synth_system.xdc
new file mode 100644
index 0000000..5748466
--- /dev/null
+++ b/scripts/vivado/synth_system.xdc
@@ -0,0 +1,34 @@
+
+# XDC File for Basys3 Board
+###########################
+
+set_property PACKAGE_PIN W5 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+create_clock -period 10.00 [get_ports clk]
+
+# Pmod Header JA (JA0..JA7)
+set_property PACKAGE_PIN J1 [get_ports {out_byte[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[0]}]
+set_property PACKAGE_PIN L2 [get_ports {out_byte[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[1]}]
+set_property PACKAGE_PIN J2 [get_ports {out_byte[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[2]}]
+set_property PACKAGE_PIN G2 [get_ports {out_byte[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[3]}]
+set_property PACKAGE_PIN H1 [get_ports {out_byte[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[4]}]
+set_property PACKAGE_PIN K2 [get_ports {out_byte[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[5]}]
+set_property PACKAGE_PIN H2 [get_ports {out_byte[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[6]}]
+set_property PACKAGE_PIN G3 [get_ports {out_byte[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte[7]}]
+
+# Pmod Header JB (JB0..JB2)
+set_property PACKAGE_PIN A14 [get_ports {resetn}]
+set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
+set_property PACKAGE_PIN A16 [get_ports {trap}]
+set_property IOSTANDARD LVCMOS33 [get_ports {trap}]
+set_property PACKAGE_PIN B15 [get_ports {out_byte_en}]
+set_property IOSTANDARD LVCMOS33 [get_ports {out_byte_en}]
+
diff --git a/scripts/vivado/system.v b/scripts/vivado/system.v
new file mode 100644
index 0000000..86449a0
--- /dev/null
+++ b/scripts/vivado/system.v
@@ -0,0 +1,65 @@
+`timescale 1 ns / 1 ps
+
+module system (
+	input            clk,
+	input            resetn,
+	output           trap,
+	output reg [7:0] out_byte,
+	output reg       out_byte_en
+);
+	// 4096 32bit words = 16kB memory
+	parameter MEM_SIZE = 4096;
+
+	wire mem_valid;
+	wire mem_instr;
+	wire mem_ready;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [3:0] mem_wstrb;
+	reg [31:0] mem_rdata;
+
+	wire mem_la_read;
+	wire mem_la_write;
+	wire [31:0] mem_la_addr;
+	wire [31:0] mem_la_wdata;
+	wire [3:0] mem_la_wstrb;
+
+	picorv32 uut (
+		.clk         (clk         ),
+		.resetn      (resetn      ),
+		.trap        (trap        ),
+		.mem_valid   (mem_valid   ),
+		.mem_instr   (mem_instr   ),
+		.mem_ready   (mem_ready   ),
+		.mem_addr    (mem_addr    ),
+		.mem_wdata   (mem_wdata   ),
+		.mem_wstrb   (mem_wstrb   ),
+		.mem_rdata   (mem_rdata   ),
+		.mem_la_read (mem_la_read ),
+		.mem_la_write(mem_la_write),
+		.mem_la_addr (mem_la_addr ),
+		.mem_la_wdata(mem_la_wdata),
+		.mem_la_wstrb(mem_la_wstrb)
+	);
+
+	reg [31:0] memory [0:MEM_SIZE-1];
+	initial $readmemh("firmware.hex", memory);
+
+	assign mem_ready = 1;
+
+	always @(posedge clk) begin
+		out_byte_en <= 0;
+		mem_rdata <= memory[mem_la_addr >> 2];
+		if (mem_la_write && (mem_la_addr >> 2) < MEM_SIZE) begin
+			if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0];
+			if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8];
+			if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16];
+			if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24];
+		end
+		else
+		if (mem_la_write && mem_la_addr == 32'h1000_0000) begin
+			out_byte_en <= 1;
+			out_byte <= mem_la_wdata;
+		end
+	end
+endmodule
diff --git a/scripts/vivado/system_tb.v b/scripts/vivado/system_tb.v
new file mode 100644
index 0000000..f0676ca
--- /dev/null
+++ b/scripts/vivado/system_tb.v
@@ -0,0 +1,34 @@
+`timescale 1 ns / 1 ps
+
+module system_tb;
+	reg clk = 1;
+	always #5 clk = ~clk;
+
+	reg resetn = 0;
+	initial begin
+		repeat (100) @(posedge clk);
+		resetn <= 1;
+	end
+
+	wire trap;
+	wire [7:0] out_byte;
+	wire out_byte_en;
+
+	system uut (
+		.clk        (clk        ),
+		.resetn     (resetn     ),
+		.trap       (trap       ),
+		.out_byte   (out_byte   ),
+		.out_byte_en(out_byte_en)
+	);
+
+	always @(posedge clk) begin
+		if (resetn && out_byte_en) begin
+			$write("%c", out_byte);
+			$fflush;
+		end
+		if (resetn && trap) begin
+			$finish;
+		end
+	end
+endmodule
-- 
cgit