From d124abbacd655e449becb9a05cb70ff45c50fa9b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 9 Aug 2019 09:23:17 +0200 Subject: Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index c22cb0c..3f41f0c 100644 --- a/README.md +++ b/README.md @@ -92,7 +92,7 @@ This Verilog file contains the following Verilog modules: | `picorv32_axi` | The version of the CPU with AXI4-Lite interface | | `picorv32_axi_adapter` | Adapter from PicoRV32 Memory Interface to AXI4-Lite | | `picorv32_wb` | The version of the CPU with Wishbone Master interface | -| `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU|U]]` instructions | +| `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU\|U]]` instructions | | `picorv32_pcpi_fast_mul` | A version of `picorv32_pcpi_fast_mul` using a single cycle multiplier | | `picorv32_pcpi_div` | A PCPI core that implements the `DIV[U]/REM[U]` instructions | -- cgit