From d21937bafc77e9f7d81c2f50d2ad825a39fb644c Mon Sep 17 00:00:00 2001 From: Steffen Vogel Date: Mon, 11 Feb 2019 23:13:05 +0100 Subject: picosoc: increase available memory by using SPRAM instead of BRAM for the Icebreaker example --- picosoc/Makefile | 6 ++-- picosoc/ice40up5k_spram.v | 91 +++++++++++++++++++++++++++++++++++++++++++++++ picosoc/icebreaker.v | 9 ++++- picosoc/picosoc.core | 6 +++- picosoc/picosoc.v | 12 ++++++- 5 files changed, 118 insertions(+), 6 deletions(-) create mode 100644 picosoc/ice40up5k_spram.v diff --git a/picosoc/Makefile b/picosoc/Makefile index aee1195..29a3b07 100644 --- a/picosoc/Makefile +++ b/picosoc/Makefile @@ -5,7 +5,7 @@ hx8ksim: hx8kdemo_tb.vvp hx8kdemo_fw.hex vvp -N $< +firmware=hx8kdemo_fw.hex hx8ksynsim: hx8kdemo_syn_tb.vvp hx8kdemo_fw.hex - vvp -N $< +firmware=hx8kdemo_fw.hex + vvp -N $< +firmware=hx8kdemo_fw.hex hx8kdemo.blif: hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -blif hx8kdemo.blif' $^ @@ -50,10 +50,10 @@ icebsim: icebreaker_tb.vvp icebreaker_fw.hex icebsynsim: icebreaker_syn_tb.vvp icebreaker_fw.hex vvp -N $< +firmware=icebreaker_fw.hex -icebreaker.json: icebreaker.v spimemio.v simpleuart.v picosoc.v ../picorv32.v +icebreaker.json: icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.v ../picorv32.v yosys -ql icebreaker.log -p 'synth_ice40 -top icebreaker -json icebreaker.json' $^ -icebreaker_tb.vvp: icebreaker_tb.v icebreaker.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v +icebreaker_tb.vvp: icebreaker_tb.v icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` icebreaker_syn_tb.vvp: icebreaker_tb.v icebreaker_syn.v spiflash.v diff --git a/picosoc/ice40up5k_spram.v b/picosoc/ice40up5k_spram.v new file mode 100644 index 0000000..6edb23b --- /dev/null +++ b/picosoc/ice40up5k_spram.v @@ -0,0 +1,91 @@ + +/* + * PicoSoC - A simple example SoC using PicoRV32 + * + * Copyright (C) 2017 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +module ice40up5k_spram #( + // We current always use the whole SPRAM (128 kB) + parameter integer WORDS = 32768 +) ( + input clk, + input [3:0] wen, + input [21:0] addr, + input [31:0] wdata, + output [31:0] rdata +); + + wire cs_0, cs_1; + wire [31:0] rdata_0, rdata_1; + + assign cs_0 = !addr[14]; + assign cs_1 = addr[14]; + assign rdata = addr[14] ? rdata_1 : rdata_0; + + SB_SPRAM256KA ram00 ( + .ADDRESS(addr[13:0]), + .DATAIN(wdata[15:0]), + .MASKWREN({wen[1], wen[1], wen[0], wen[0]}), + .WREN(wen[1]|wen[0]), + .CHIPSELECT(cs_0), + .CLOCK(clk), + .STANDBY(1'b0), + .SLEEP(1'b0), + .POWEROFF(1'b1), + .DATAOUT(rdata_0[15:0]) + ); + + SB_SPRAM256KA ram01 ( + .ADDRESS(addr[13:0]), + .DATAIN(wdata[31:16]), + .MASKWREN({wen[3], wen[3], wen[2], wen[2]}), + .WREN(wen[3]|wen[2]), + .CHIPSELECT(cs_0), + .CLOCK(clk), + .STANDBY(1'b0), + .SLEEP(1'b0), + .POWEROFF(1'b1), + .DATAOUT(rdata_0[31:16]) + ); + + SB_SPRAM256KA ram10 ( + .ADDRESS(addr[13:0]), + .DATAIN(wdata[15:0]), + .MASKWREN({wen[1], wen[1], wen[0], wen[0]}), + .WREN(wen[1]|wen[0]), + .CHIPSELECT(cs_1), + .CLOCK(clk), + .STANDBY(1'b0), + .SLEEP(1'b0), + .POWEROFF(1'b1), + .DATAOUT(rdata_1[15:0]) + ); + + SB_SPRAM256KA ram11 ( + .ADDRESS(addr[13:0]), + .DATAIN(wdata[31:16]), + .MASKWREN({wen[3], wen[3], wen[2], wen[2]}), + .WREN(wen[3]|wen[2]), + .CHIPSELECT(cs_1), + .CLOCK(clk), + .STANDBY(1'b0), + .SLEEP(1'b0), + .POWEROFF(1'b1), + .DATAOUT(rdata_1[31:16]) + ); + +endmodule diff --git a/picosoc/icebreaker.v b/picosoc/icebreaker.v index ef9b9ac..00da2d7 100644 --- a/picosoc/icebreaker.v +++ b/picosoc/icebreaker.v @@ -17,6 +17,12 @@ * */ +`ifdef PICOSOC_V +`error "icebreaker.v must be read before icebreaker.v!" +`endif + +`define PICOSOC_MEM ice40up5k_spram + module icebreaker ( input clk, @@ -100,7 +106,8 @@ module icebreaker ( picosoc #( .BARREL_SHIFTER(0), - .ENABLE_MULDIV(0) + .ENABLE_MULDIV(0), + .MEM_WORDS(32768) ) soc ( .clk (clk ), .resetn (resetn ), diff --git a/picosoc/picosoc.core b/picosoc/picosoc.core index a6eae08..eb0988a 100644 --- a/picosoc/picosoc.core +++ b/picosoc/picosoc.core @@ -14,10 +14,14 @@ filesets: targets: default: filesets : [picosoc] - parameters : [PICORV32_REGS] + parameters : [PICORV32_REGS, PICOSOC_MEM] parameters: PICORV32_REGS: datatype : str default : picosoc_regs paramtype : vlogdefine + PICOSOC_MEM: + datatype : str + default : picosoc_mem + paramtype : vlogdefine diff --git a/picosoc/picosoc.v b/picosoc/picosoc.v index 353f2ef..9c5981e 100644 --- a/picosoc/picosoc.v +++ b/picosoc/picosoc.v @@ -25,6 +25,14 @@ `define PICORV32_REGS picosoc_regs `endif +`ifndef PICOSOC_MEM +`define PICOSOC_MEM picosoc_mem +`endif + +// this macro can be used to check if the verilog files in your +// design are read in the correct order. +`define PICOSOC_V + module picosoc ( input clk, input resetn, @@ -197,7 +205,9 @@ module picosoc ( always @(posedge clk) ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS; - picosoc_mem #(.WORDS(MEM_WORDS)) memory ( + `PICOSOC_MEM #( + .WORDS(MEM_WORDS) + ) memory ( .clk(clk), .wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0), .addr(mem_addr[23:2]), -- cgit