From 0bea8428f342a455c5ca720cbac02be111da7120 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 15 Dec 2016 12:51:31 +0100 Subject: Suppress iverilog warnings re parameters in "make test_synth" --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index b1e3c66..4402ae9 100644 --- a/Makefile +++ b/Makefile @@ -49,7 +49,7 @@ testbench_sp.vvp: testbench.v picorv32.v chmod -x testbench_sp.vvp testbench_synth.vvp: testbench.v synth.v - iverilog -o testbench_synth.vvp testbench.v synth.v + iverilog -o testbench_synth.vvp -DSYNTH_TEST testbench.v synth.v chmod -x testbench_synth.vvp synth.v: picorv32.v scripts/yosys/synth_sim.ys -- cgit