From 4792ef3945245b29faaad734e8b3a4b3f3a82f14 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 12 Apr 2016 18:23:32 +0200 Subject: Added "picorv32_pcpi_div" module to README.md --- README.md | 1 + 1 file changed, 1 insertion(+) (limited to 'README.md') diff --git a/README.md b/README.md index c585984..30dc67d 100644 --- a/README.md +++ b/README.md @@ -91,6 +91,7 @@ This Verilog file contains the following Verilog modules: | `picorv32_axi` | The version of the CPU with AXI4-Lite interface | | `picorv32_axi_adapter` | Adapter from PicoRV32 Memory Interface to AXI4-Lite | | `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU|U]]` instructions | +| `picorv32_pcpi_div` | A PCPI core that implements the `DIV[U]/REM[U]` instructions | Simply copy this file into your project. -- cgit