From 490a7345191f9841fa953d18b27c8485171406ce Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 1 Jun 2016 12:39:00 +0200 Subject: Encode in q0 LSB if interrupted instruction is compressed --- README.md | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index cdd6776..d3a7588 100644 --- a/README.md +++ b/README.md @@ -463,6 +463,10 @@ address and `q1` contains a bitmask of all IRQs to be handled. This means one call to the interrupt handler needs to service more than one IRQ when more than one bit is set in `q1`. +When support for compressed instructions is enabled, then the LSB of q0 is set +when the interrupted instruction is a compressed instruction. This can be used if +the IRQ handler wants to decode the interrupted instruction. + Registers `q2` and `q3` are uninitialized and can be used as temporary storage when saving/restoring register values in the IRQ handler. -- cgit