From 8043c90a04031c1619d0be7b1aba717e4f9968ac Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 24 Aug 2016 15:20:23 +0200 Subject: Added REGS_INIT_ZERO parameter --- README.md | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'README.md') diff --git a/README.md b/README.md index 6c6e060..51eb17e 100644 --- a/README.md +++ b/README.md @@ -256,6 +256,11 @@ Set this to 0 to disable support for the `timer` instruction. Support for the timer is always disabled when ENABLE_IRQ is set to 0. +#### REGS_INIT_ZERO (default = 0) + +Set this to 1 to initialize all registers to zero (using a Verilog `initial` block). +This can be useful for simulation or formal verification. + #### MASKED_IRQ (default = 32'h 0000_0000) A 1 bit in this bitmask corresponds to a permanently disabled IRQ. -- cgit