From f4bb91b060211884fc0b85479fb6becf20daeb1f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 6 Jun 2016 10:46:52 +0200 Subject: RISC-V ISA 2.1 now calls "sbreak" officially "ebreak" --- README.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index d3a7588..266eea1 100644 --- a/README.md +++ b/README.md @@ -215,9 +215,9 @@ accesses. Set this to 0 to disable the circuitry for catching illegal instructions. -The core will still trap on an `SBREAK` instruction with this option -set to 0. With IRQs enabled, an `SBREAK` normally triggers an IRQ 1. With -this option set to 0, an `SBREAK` will trap the processor without +The core will still trap on `EBREAK` instructions with this option +set to 0. With IRQs enabled, an `EBREAK` normally triggers an IRQ 1. With +this option set to 0, an `EBREAK` will trap the processor without triggering an interrupt. #### ENABLE_PCPI (default = 0) @@ -448,11 +448,11 @@ interrupt handler returns. The IRQs 0-2 can be triggered internally by the following built-in interrupt sources: -| IRQ | Interrupt Source | -| ---:| -----------------------------------| -| 0 | Timer Interrupt | -| 1 | SBREAK or Illegal Instruction | -| 2 | BUS Error (Unalign Memory Access) | +| IRQ | Interrupt Source | +| ---:| ------------------------------------| +| 0 | Timer Interrupt | +| 1 | EBREAK/ECALL or Illegal Instruction | +| 2 | BUS Error (Unalign Memory Access) | This interrupts can also be triggered by external sources, such as co-processors connected via PCPI. -- cgit