From 323d77ba5deddd2411699e77f4091612edaf2012 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 13 Apr 2016 19:52:52 +0200 Subject: Fixed "make timing" in dhrystone/ --- dhrystone/testbench.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'dhrystone') diff --git a/dhrystone/testbench.v b/dhrystone/testbench.v index 6a03ca0..aa32619 100644 --- a/dhrystone/testbench.v +++ b/dhrystone/testbench.v @@ -91,8 +91,9 @@ module testbench; repeat (100000) @(posedge clk); $finish; end - always @(uut.count_instr[0]) begin - $display("## %-s %d", uut.ascii_instr ? uut.ascii_instr : "x", uut.count_cycle); + always @(posedge clk) begin + if (uut.decoder_trigger_q && !uut.decoder_pseudo_trigger_q) + $display("## %-s %d", uut.dbg_ascii_instr ? uut.dbg_ascii_instr : "x", uut.count_cycle); end `endif endmodule -- cgit