From 85d8401c3d79fd913d83e6975ec873649453b1f2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 4 Sep 2016 12:27:38 +0200 Subject: Renamed testbench_slow_mem to testbench_nola (no look ahead) --- dhrystone/Makefile | 12 +++--- dhrystone/testbench_nola.v | 95 ++++++++++++++++++++++++++++++++++++++++++ dhrystone/testbench_slow_mem.v | 93 ----------------------------------------- 3 files changed, 101 insertions(+), 99 deletions(-) create mode 100644 dhrystone/testbench_nola.v delete mode 100644 dhrystone/testbench_slow_mem.v (limited to 'dhrystone') diff --git a/dhrystone/Makefile b/dhrystone/Makefile index 88cbf4d..3b282f0 100644 --- a/dhrystone/Makefile +++ b/dhrystone/Makefile @@ -13,8 +13,8 @@ endif test: testbench.vvp dhry.hex vvp -N testbench.vvp -test_slow_mem: testbench_slow_mem.vvp dhry.hex - vvp -N testbench_slow_mem.vvp +test_nola: testbench_nola.vvp dhry.hex + vvp -N testbench_nola.vvp timing: timing.txt grep '^##' timing.txt | gawk 'x != "" {print x,$$3-y;} {x=$$2;y=$$3;}' | sort | uniq -c | \ @@ -27,9 +27,9 @@ testbench.vvp: testbench.v ../picorv32.v iverilog -o testbench.vvp testbench.v ../picorv32.v chmod -x testbench.vvp -testbench_slow_mem.vvp: testbench_slow_mem.v ../picorv32.v - iverilog -o testbench_slow_mem.vvp testbench_slow_mem.v ../picorv32.v - chmod -x testbench_slow_mem.vvp +testbench_nola.vvp: testbench_nola.v ../picorv32.v + iverilog -o testbench_nola.vvp testbench_nola.v ../picorv32.v + chmod -x testbench_nola.vvp timing.vvp: testbench.v ../picorv32.v iverilog -o timing.vvp -DTIMING testbench.v ../picorv32.v @@ -57,7 +57,7 @@ endif dhry_1.o dhry_2.o: CFLAGS += -Wno-implicit-int -Wno-implicit-function-declaration clean: - rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.vvp testbench.vcd timing.vvp timing.txt testbench_slow_mem.vvp + rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.vvp testbench.vcd timing.vvp timing.txt testbench_nola.vvp .PHONY: test clean diff --git a/dhrystone/testbench_nola.v b/dhrystone/testbench_nola.v new file mode 100644 index 0000000..b1a154c --- /dev/null +++ b/dhrystone/testbench_nola.v @@ -0,0 +1,95 @@ +// A version of the dhrystone test bench that isn't using the look-ahead interface + +`timescale 1 ns / 1 ps + +module testbench; + reg clk = 1; + reg resetn = 0; + wire trap; + + always #5 clk = ~clk; + + initial begin + repeat (100) @(posedge clk); + resetn <= 1; + end + + wire mem_valid; + wire mem_instr; + reg mem_ready; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [3:0] mem_wstrb; + reg [31:0] mem_rdata; + + picorv32 #( + .BARREL_SHIFTER(1), + .ENABLE_FAST_MUL(1), + .ENABLE_DIV(1), + .PROGADDR_RESET('h10000), + .STACKADDR('h10000) + ) uut ( + .clk (clk ), + .resetn (resetn ), + .trap (trap ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ) + ); + + reg [7:0] memory [0:256*1024-1]; + initial $readmemh("dhry.hex", memory); + + always @(posedge clk) begin + mem_ready <= 1'b0; + + mem_rdata[ 7: 0] <= 'bx; + mem_rdata[15: 8] <= 'bx; + mem_rdata[23:16] <= 'bx; + mem_rdata[31:24] <= 'bx; + + if (mem_valid & !mem_ready) begin + if (|mem_wstrb) begin + mem_ready <= 1'b1; + + case (mem_addr) + 32'h1000_0000: begin + $write("%c", mem_wdata); + $fflush(); + end + default: begin + if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0]; + if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8]; + if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16]; + if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24]; + end + endcase + end + else begin + mem_ready <= 1'b1; + + mem_rdata[ 7: 0] <= memory[mem_addr + 0]; + mem_rdata[15: 8] <= memory[mem_addr + 1]; + mem_rdata[23:16] <= memory[mem_addr + 2]; + mem_rdata[31:24] <= memory[mem_addr + 3]; + end + end + end + + initial begin + $dumpfile("testbench_nola.vcd"); + $dumpvars(0, testbench); + end + + always @(posedge clk) begin + if (resetn && trap) begin + repeat (10) @(posedge clk); + $display("TRAP"); + $finish; + end + end +endmodule diff --git a/dhrystone/testbench_slow_mem.v b/dhrystone/testbench_slow_mem.v deleted file mode 100644 index 305cb81..0000000 --- a/dhrystone/testbench_slow_mem.v +++ /dev/null @@ -1,93 +0,0 @@ -`timescale 1 ns / 1 ps - -module testbench; - reg clk = 1; - reg resetn = 0; - wire trap; - - always #5 clk = ~clk; - - initial begin - repeat (100) @(posedge clk); - resetn <= 1; - end - - wire mem_valid; - wire mem_instr; - reg mem_ready; - wire [31:0] mem_addr; - wire [31:0] mem_wdata; - wire [3:0] mem_wstrb; - reg [31:0] mem_rdata; - - picorv32 #( - .BARREL_SHIFTER(1), - .ENABLE_FAST_MUL(1), - .ENABLE_DIV(1), - .PROGADDR_RESET('h10000), - .STACKADDR('h10000) - ) uut ( - .clk (clk ), - .resetn (resetn ), - .trap (trap ), - .mem_valid (mem_valid ), - .mem_instr (mem_instr ), - .mem_ready (mem_ready ), - .mem_addr (mem_addr ), - .mem_wdata (mem_wdata ), - .mem_wstrb (mem_wstrb ), - .mem_rdata (mem_rdata ) - ); - - reg [7:0] memory [0:256*1024-1]; - initial $readmemh("dhry.hex", memory); - - always @(posedge clk) begin - mem_ready <= 1'b0; - - mem_rdata[ 7: 0] <= 'bx; - mem_rdata[15: 8] <= 'bx; - mem_rdata[23:16] <= 'bx; - mem_rdata[31:24] <= 'bx; - - if (mem_valid & !mem_ready) begin - if (|mem_wstrb) begin - mem_ready <= 1'b1; - - case (mem_addr) - 32'h1000_0000: begin - $write("%c", mem_wdata); - $fflush(); - end - default: begin - if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0]; - if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8]; - if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16]; - if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24]; - end - endcase - end - else begin - mem_ready <= 1'b1; - - mem_rdata[ 7: 0] <= memory[mem_addr + 0]; - mem_rdata[15: 8] <= memory[mem_addr + 1]; - mem_rdata[23:16] <= memory[mem_addr + 2]; - mem_rdata[31:24] <= memory[mem_addr + 3]; - end - end - end - - initial begin - $dumpfile("testbench_slow_mem.vcd"); - $dumpvars(0, testbench); - end - - always @(posedge clk) begin - if (resetn && trap) begin - repeat (10) @(posedge clk); - $display("TRAP"); - $finish; - end - end -endmodule -- cgit