From a9532f81edc0211e404f5c0cf4348bd55b6d9674 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 8 Jun 2015 08:59:40 +0200 Subject: Refactored instruction decoder --- dhrystone/testbench.v | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'dhrystone') diff --git a/dhrystone/testbench.v b/dhrystone/testbench.v index 9e0d329..c3c766d 100644 --- a/dhrystone/testbench.v +++ b/dhrystone/testbench.v @@ -50,8 +50,7 @@ module testbench; assign mem_ready = 1; always @(posedge clk) begin - if (mem_la_read) - mem_rdata <= memory[mem_la_addr >> 2]; + mem_rdata <= mem_la_read ? memory[mem_la_addr >> 2] : 'bx; if (mem_la_write) begin case (mem_la_addr) 32'h1000_0000: begin -- cgit