From 9201bff2ef56b66e10dc9c56fe431b6f436f0c8f Mon Sep 17 00:00:00 2001 From: Tom Verbeure Date: Mon, 29 Aug 2016 18:00:49 -0700 Subject: Reduce rs1, rs2 from 64 to 33 bits to make life for synthesis tools easier. --- picorv32.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'picorv32.v') diff --git a/picorv32.v b/picorv32.v index d4fb656..2af50e8 100644 --- a/picorv32.v +++ b/picorv32.v @@ -1889,7 +1889,8 @@ module picorv32_pcpi_fast_mul ( wire instr_rs2_signed = |{instr_mulh}; reg active1, active2, shift_out; - reg [63:0] rs1, rs2, rd; + reg [32:0] rs1, rs2; + reg [63:0] rd; always @* begin instr_mul = 0; -- cgit From cefe09b8d41285d3ece4ab0efcfe6aea1a259cd8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 30 Aug 2016 11:12:16 +0200 Subject: Minor fixes/cleanups in mul reset logic --- picorv32.v | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'picorv32.v') diff --git a/picorv32.v b/picorv32.v index d4fb656..0f7ce79 100644 --- a/picorv32.v +++ b/picorv32.v @@ -1862,7 +1862,7 @@ module picorv32_pcpi_mul #( always @(posedge clk) begin pcpi_wr <= 0; pcpi_ready <= 0; - if (mul_finish) begin + if (mul_finish && resetn) begin pcpi_wr <= 1; pcpi_ready <= 1; pcpi_rd <= instr_any_mulh ? rd >> 32 : rd; @@ -1928,6 +1928,11 @@ module picorv32_pcpi_fast_mul ( end active2 <= active1; shift_out <= instr_any_mulh; + + if (!resetn) begin + active1 <= 0; + active2 <= 0; + end end assign pcpi_wr = active2; -- cgit From bfba9b3eb34bfd9cc5d516153ddc960a44f7c5f2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 30 Aug 2016 11:14:46 +0200 Subject: Bugfix in picorv32_pcpi_fast_mul --- picorv32.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'picorv32.v') diff --git a/picorv32.v b/picorv32.v index fe45e18..d8c088f 100644 --- a/picorv32.v +++ b/picorv32.v @@ -1909,7 +1909,7 @@ module picorv32_pcpi_fast_mul ( end always @(posedge clk) begin - rd <= rs1 * rs2; + rd <= $signed(rs1) * $signed(rs2); end always @(posedge clk) begin -- cgit