From d26e505251dffc4deca4e7b38fb3049a6d39644a Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Fri, 11 May 2018 22:56:52 +0200 Subject: Fix spiflash_tb Update expected two first Flash words to reflect changes in start.s Add dummy SPI cycles to account for latency --- picosoc/spiflash_tb.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'picosoc') diff --git a/picosoc/spiflash_tb.v b/picosoc/spiflash_tb.v index ce2e949..f300373 100644 --- a/picosoc/spiflash_tb.v +++ b/picosoc/spiflash_tb.v @@ -53,8 +53,8 @@ module testbench; ); localparam [23:0] offset = 24'h100000; - localparam [31:0] word0 = 32'h 01300293; - localparam [31:0] word1 = 32'h 00502223; + localparam [31:0] word0 = 32'h 00000093; + localparam [31:0] word1 = 32'h 00000193; reg [7:0] rdata; integer errcount = 0; @@ -291,7 +291,7 @@ module testbench; xfer_qspi_wr(offset[15:8]); xfer_qspi_wr(offset[7:0]); xfer_qspi_wr(8'h a5); - xfer_dummy; + repeat (8) xfer_dummy; xfer_qspi_rd; expect(word0[7:0]); xfer_qspi_rd; expect(word0[15:8]); xfer_qspi_rd; expect(word0[23:16]); @@ -308,7 +308,7 @@ module testbench; xfer_qspi_wr(offset[15:8]); xfer_qspi_wr(offset[7:0]); xfer_qspi_wr(8'h ff); - xfer_dummy; + repeat (8) xfer_dummy; xfer_qspi_rd; expect(word0[7:0]); xfer_qspi_rd; expect(word0[15:8]); xfer_qspi_rd; expect(word0[23:16]); @@ -326,7 +326,7 @@ module testbench; xfer_qspi_ddr_wr(offset[15:8]); xfer_qspi_ddr_wr(offset[7:0]); xfer_qspi_ddr_wr(8'h a5); - xfer_dummy; + repeat (8) xfer_dummy; xfer_qspi_ddr_rd; expect(word0[7:0]); xfer_qspi_ddr_rd; expect(word0[15:8]); xfer_qspi_ddr_rd; expect(word0[23:16]); @@ -343,7 +343,7 @@ module testbench; xfer_qspi_ddr_wr(offset[15:8]); xfer_qspi_ddr_wr(offset[7:0]); xfer_qspi_ddr_wr(8'h ff); - xfer_dummy; + repeat (8) xfer_dummy; xfer_qspi_ddr_rd; expect(word0[7:0]); xfer_qspi_ddr_rd; expect(word0[15:8]); xfer_qspi_ddr_rd; expect(word0[23:16]); -- cgit