From 8d404182b32d70c4b1bbb21ebb885b4671f60819 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 4 Jul 2015 16:34:18 +0200
Subject: Improved IceStorm example script

---
 scripts/icestorm/.gitignore |  3 ++
 scripts/icestorm/build.sh   |  3 +-
 scripts/icestorm/top.v      | 70 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 75 insertions(+), 1 deletion(-)
 create mode 100644 scripts/icestorm/top.v

(limited to 'scripts/icestorm')

diff --git a/scripts/icestorm/.gitignore b/scripts/icestorm/.gitignore
index 9542efe..9502e6b 100644
--- a/scripts/icestorm/.gitignore
+++ b/scripts/icestorm/.gitignore
@@ -1,2 +1,5 @@
 synth.blif
 synth.log
+synth.bin
+synth.txt
+firmware.hex
diff --git a/scripts/icestorm/build.sh b/scripts/icestorm/build.sh
index dcd6fb6..cdefd04 100644
--- a/scripts/icestorm/build.sh
+++ b/scripts/icestorm/build.sh
@@ -1,5 +1,6 @@
 #!/bin/bash
 set -ex
-yosys -ql synth.log -p 'synth_ice40 -blif synth.blif' ../../picorv32.v
+echo -n > firmware.hex
+yosys -l synth.log -p 'synth_ice40 -top top -blif synth.blif' ../../picorv32.v top.v
 arachne-pnr -d 8k -o synth.txt synth.blif
 icepack synth.txt synth.bin
diff --git a/scripts/icestorm/top.v b/scripts/icestorm/top.v
new file mode 100644
index 0000000..026321d
--- /dev/null
+++ b/scripts/icestorm/top.v
@@ -0,0 +1,70 @@
+`timescale 1 ns / 1 ps
+
+module top (
+	input            clk,
+	input            resetn,
+	output           trap,
+	output reg [7:0] out_byte,
+	output reg       out_byte_en
+);
+	// 1024 32bit words = 4kB memory
+	parameter MEM_SIZE = 1024;
+
+	wire mem_valid;
+	wire mem_instr;
+	wire mem_ready;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [3:0] mem_wstrb;
+	reg [31:0] mem_rdata;
+
+	wire mem_la_read;
+	wire mem_la_write;
+	wire [31:0] mem_la_addr;
+	wire [31:0] mem_la_wdata;
+	wire [3:0] mem_la_wstrb;
+
+	picorv32 #(
+		.ENABLE_COUNTERS(0),
+		.TWO_STAGE_SHIFT(0),
+		.CATCH_MISALIGN(0),
+		.CATCH_ILLINSN(0)
+	) uut (
+		.clk         (clk         ),
+		.resetn      (resetn      ),
+		.trap        (trap        ),
+		.mem_valid   (mem_valid   ),
+		.mem_instr   (mem_instr   ),
+		.mem_ready   (mem_ready   ),
+		.mem_addr    (mem_addr    ),
+		.mem_wdata   (mem_wdata   ),
+		.mem_wstrb   (mem_wstrb   ),
+		.mem_rdata   (mem_rdata   ),
+		.mem_la_read (mem_la_read ),
+		.mem_la_write(mem_la_write),
+		.mem_la_addr (mem_la_addr ),
+		.mem_la_wdata(mem_la_wdata),
+		.mem_la_wstrb(mem_la_wstrb)
+	);
+
+	reg [31:0] memory [0:MEM_SIZE-1];
+	initial $readmemh("firmware.hex", memory);
+
+	assign mem_ready = 1;
+
+	always @(posedge clk) begin
+		out_byte_en <= 0;
+		mem_rdata <= memory[mem_la_addr >> 2];
+		if (mem_la_write && (mem_la_addr >> 2) < MEM_SIZE) begin
+			if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0];
+			if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8];
+			if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16];
+			if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24];
+		end
+		else
+		if (mem_la_write && mem_la_addr == 32'h1000_0000) begin
+			out_byte_en <= 1;
+			out_byte <= mem_la_wdata;
+		end
+	end
+endmodule
-- 
cgit