From 997c5ce341ce4fcc209992a9b9096651e767eb2d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 30 Jun 2015 01:46:25 +0200 Subject: Added "make test_synth" --- scripts/yosys/synth_sim.ys | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 scripts/yosys/synth_sim.ys (limited to 'scripts/yosys/synth_sim.ys') diff --git a/scripts/yosys/synth_sim.ys b/scripts/yosys/synth_sim.ys new file mode 100644 index 0000000..b64e7e1 --- /dev/null +++ b/scripts/yosys/synth_sim.ys @@ -0,0 +1,7 @@ +# yosys synthesis script for post-synthesis simulation (make test_synth) + +read_verilog picorv32.v +chparam -set ENABLE_IRQ 1 -set ENABLE_MUL 1 picorv32_axi +hierarchy -top picorv32_axi +synth +write_verilog synth.v -- cgit