From ca5702c75f50c2aba17d1495039fdcbab13f8987 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 15 Dec 2016 12:48:57 +0100
Subject: Fixed "make test_synth"

---
 scripts/yosys/synth_sim.ys | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'scripts/yosys/synth_sim.ys')

diff --git a/scripts/yosys/synth_sim.ys b/scripts/yosys/synth_sim.ys
index b64e7e1..ded89d9 100644
--- a/scripts/yosys/synth_sim.ys
+++ b/scripts/yosys/synth_sim.ys
@@ -1,7 +1,8 @@
 # yosys synthesis script for post-synthesis simulation (make test_synth)
 
 read_verilog picorv32.v
-chparam -set ENABLE_IRQ 1 -set ENABLE_MUL 1 picorv32_axi
+chparam -set COMPRESSED_ISA 1 -set ENABLE_MUL 1 -set ENABLE_DIV 1 \
+        -set ENABLE_IRQ 1 -set ENABLE_TRACE 1 picorv32_axi
 hierarchy -top picorv32_axi
 synth
 write_verilog synth.v
-- 
cgit