From 3f9b5048bc26e3fa1cf7d13504f502d28ee99051 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 22 Sep 2019 13:59:43 +0200
Subject: Fix initialization of "irq" in verilog testbench

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 testbench.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'testbench.v')

diff --git a/testbench.v b/testbench.v
index eee2676..9d8e249 100644
--- a/testbench.v
+++ b/testbench.v
@@ -75,7 +75,7 @@ module picorv32_wrapper #(
 	output [35:0] trace_data
 );
 	wire tests_passed;
-	reg [31:0] irq;
+	reg [31:0] irq = 0;
 
 	reg [15:0] count_cycle = 0;
 	always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0;
-- 
cgit