From 9591ae9f7d4182463a2a3af2a51212d29f9781bf Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Thu, 18 Feb 2016 22:42:01 +0100
Subject: Split out verilator-incompatible code to top-level testbench

Verilator doesn't handle verilog code that deals with time, such
as delayed signals or the repeat task. Clock and reset generation
are therefore moved to a separate file that can be replaced by
a verilator module. VCD generation is also affected by this.
---
 testbench.v | 106 ++++--------------------------------------------------------
 1 file changed, 7 insertions(+), 99 deletions(-)

(limited to 'testbench.v')

diff --git a/testbench.v b/testbench.v
index af3156e..404c9c1 100644
--- a/testbench.v
+++ b/testbench.v
@@ -15,14 +15,6 @@ module testbench #(
 
 	reg clk = 1;
 	reg resetn = 0;
-	reg [31:0] irq;
-	wire trap;
-
-	always @* begin
-		irq = 0;
-		irq[4] = &uut.picorv32_core.count_cycle[12:0];
-		irq[5] = &uut.picorv32_core.count_cycle[15:0];
-	end
 
 	always #5 clk = ~clk;
 
@@ -31,88 +23,6 @@ module testbench #(
 		resetn <= 1;
 	end
 
-	wire        mem_axi_awvalid;
-	wire        mem_axi_awready;
-	wire [31:0] mem_axi_awaddr;
-	wire [ 2:0] mem_axi_awprot;
-
-	wire        mem_axi_wvalid;
-	wire        mem_axi_wready;
-	wire [31:0] mem_axi_wdata;
-	wire [ 3:0] mem_axi_wstrb;
-
-	wire        mem_axi_bvalid;
-	wire        mem_axi_bready;
-
-	wire        mem_axi_arvalid;
-	wire        mem_axi_arready;
-	wire [31:0] mem_axi_araddr;
-	wire [ 2:0] mem_axi_arprot;
-
-	wire        mem_axi_rvalid;
-	wire        mem_axi_rready;
-	wire [31:0] mem_axi_rdata;
-
-	axi4_memory #(
-		.AXI_TEST (AXI_TEST),
-		.VERBOSE  (VERBOSE)
-	) mem (
-		.clk             (clk             ),
-		.mem_axi_awvalid (mem_axi_awvalid ),
-		.mem_axi_awready (mem_axi_awready ),
-		.mem_axi_awaddr  (mem_axi_awaddr  ),
-		.mem_axi_awprot  (mem_axi_awprot  ),
-
-		.mem_axi_wvalid  (mem_axi_wvalid  ),
-		.mem_axi_wready  (mem_axi_wready  ),
-		.mem_axi_wdata   (mem_axi_wdata   ),
-		.mem_axi_wstrb   (mem_axi_wstrb   ),
-
-		.mem_axi_bvalid  (mem_axi_bvalid  ),
-		.mem_axi_bready  (mem_axi_bready  ),
-
-		.mem_axi_arvalid (mem_axi_arvalid ),
-		.mem_axi_arready (mem_axi_arready ),
-		.mem_axi_araddr  (mem_axi_araddr  ),
-		.mem_axi_arprot  (mem_axi_arprot  ),
-
-		.mem_axi_rvalid  (mem_axi_rvalid  ),
-		.mem_axi_rready  (mem_axi_rready  ),
-		.mem_axi_rdata   (mem_axi_rdata   )
-	);
-
-	picorv32_axi #(
-`ifdef SP_TEST
-		.ENABLE_REGS_DUALPORT(0),
-`endif
-		.ENABLE_MUL(1),
-		.ENABLE_IRQ(1)
-	) uut (
-		.clk            (clk            ),
-		.resetn         (resetn         ),
-		.trap           (trap           ),
-		.mem_axi_awvalid(mem_axi_awvalid),
-		.mem_axi_awready(mem_axi_awready),
-		.mem_axi_awaddr (mem_axi_awaddr ),
-		.mem_axi_awprot (mem_axi_awprot ),
-		.mem_axi_wvalid (mem_axi_wvalid ),
-		.mem_axi_wready (mem_axi_wready ),
-		.mem_axi_wdata  (mem_axi_wdata  ),
-		.mem_axi_wstrb  (mem_axi_wstrb  ),
-		.mem_axi_bvalid (mem_axi_bvalid ),
-		.mem_axi_bready (mem_axi_bready ),
-		.mem_axi_arvalid(mem_axi_arvalid),
-		.mem_axi_arready(mem_axi_arready),
-		.mem_axi_araddr (mem_axi_araddr ),
-		.mem_axi_arprot (mem_axi_arprot ),
-		.mem_axi_rvalid (mem_axi_rvalid ),
-		.mem_axi_rready (mem_axi_rready ),
-		.mem_axi_rdata  (mem_axi_rdata  ),
-		.irq            (irq            )
-	);
-
-	initial $readmemh("firmware/firmware.hex", mem.memory);
-
 	initial begin
 		if ($test$plusargs("vcd")) begin
 			$dumpfile("testbench.vcd");
@@ -123,13 +33,11 @@ module testbench #(
 		$finish;
 	end
 
-	integer cycle_counter;
-	always @(posedge clk) begin
-		cycle_counter <= resetn ? cycle_counter + 1 : 0;
-		if (resetn && trap) begin
-			repeat (10) @(posedge clk);
-			$display("TRAP after %1d clock cycles", cycle_counter);
-			$finish;
-		end
-	end
+	picorv32_wrapper #(
+		.AXI_TEST (AXI_TEST),
+		.VERBOSE  (VERBOSE)
+	) top (
+		.clk    (clk   ),
+		.resetn (resetn)
+	);
 endmodule
-- 
cgit