From c7cc32ed95644b50a1cd22e2005cacdba5b63388 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 17 Feb 2017 15:23:58 +0100
Subject: Fix verilog code for modelsim

---
 testbench.v | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'testbench.v')

diff --git a/testbench.v b/testbench.v
index 84a2fd0..e113265 100644
--- a/testbench.v
+++ b/testbench.v
@@ -12,7 +12,6 @@ module testbench #(
 	parameter AXI_TEST = 0,
 	parameter VERBOSE = 0
 );
-
 	reg clk = 1;
 	reg resetn = 0;
 	wire trap;
@@ -75,8 +74,6 @@ module picorv32_wrapper #(
 	output trace_valid,
 	output [35:0] trace_data
 );
-
-	wire trap;
 	wire tests_passed;
 	reg [31:0] irq;
 
@@ -234,7 +231,6 @@ module axi4_memory #(
 
 	output reg tests_passed
 );
-
 	reg [31:0]   memory [0:64*1024/4-1] /* verilator public */;
 	reg verbose;
 	initial verbose = $test$plusargs("verbose") || VERBOSE;
-- 
cgit