From a16a2e25e3a7ab29d8476d0f3165c9871b2f8622 Mon Sep 17 00:00:00 2001 From: John Wickerson Date: Tue, 11 Jan 2022 16:12:55 +0000 Subject: adding some text for performance evaluation section --- verified_resource_sharing.tex | 38 +++++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/verified_resource_sharing.tex b/verified_resource_sharing.tex index 9b799b4..c041988 100644 --- a/verified_resource_sharing.tex +++ b/verified_resource_sharing.tex @@ -372,7 +372,29 @@ The same sequence of events can also be understood using a timing diagram, as gi \section{Performance evaluation} -\JW{Todo.} +We now compare the performance of the hardware generated by Vericert-Fun against that generated by Vericert. Following \citet{Herklotz2020}, we use the PolyBench/C benchmark suite~\cite{polybench}. \JW{Do we have to skip any of the benchmarks? Michalis's thesis talks about skipping adi and ludcmp -- is that still the case?} We used the Icarus Verilog simulator~\cite{icarus} to determine the cycle counts of the generated designs. We used Xilinx Vivado 2017.1, targeting a Xilinx 7-series FPGA (XC7K70T) at 50MHz, to determine area usage and fmax. + +Figure~\ref{fig:results} summarises our results. The x-axis shows the impact of resource sharing on the speed of the hardware (as calculated by the cycle count divided by fmax); we see that all the data points lie very close to 1, which suggests no significant impact. On average the cycle count increases by 0.7\%; this modest increase is in line with expectations because our translation introduces an extra state per function call. The impact on fmax is similarly minimal, ranging between a 1.5\% increase and a 3.1\% decrease (0.2\% decrease on average). + +\begin{figure} +RESULTS GRAPH HERE.\par +RESULTS GRAPH HERE.\par +RESULTS GRAPH HERE.\par +RESULTS GRAPH HERE.\par +RESULTS GRAPH HERE.\par +RESULTS GRAPH HERE.\par +RESULTS GRAPH HERE.\par +RESULTS GRAPH HERE.\par +RESULTS GRAPH HERE.\par +RESULTS GRAPH HERE.\par +RESULTS GRAPH HERE.\par +RESULTS GRAPH HERE.\par +RESULTS GRAPH HERE.\par +\caption{Impact of resource sharing on the speed and area usage of generated hardware.} +\label{fig:results} +\end{figure} + +The y-axis shows the impact of resource sharing on the area usage of the hardware. On average we see a decrease in area usage of 12\%. The impact ranges from a 59\% decrease to a 6\% increase, with a 12\% decrease on average. It is hard to attribute precise reasons for this given the heuristic-driven nature of the synthesis process, but certainly the benchmarks with more function calls saw more benefit from resource sharing. \section{Proving Vericert-Fun correct} @@ -401,6 +423,14 @@ A few points that we might want to address at some point: \end{itemize} + + + + + +\bibliographystyle{ACM-Reference-Format} +\bibliography{references} + \appendix \section{Verilog output for running example} @@ -480,10 +510,4 @@ module main (clk, rst, ret, fin) endmodule \end{lstlisting} - - - -\bibliographystyle{ACM-Reference-Format} -\bibliography{references} - \end{document} -- cgit