From f9ca386bda2fe89287b9bb65d3d28e0c150d8984 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Thu, 7 Oct 2021 13:43:16 +0100
Subject: Add initial files

---
 paper/data/example_gen.v | 56 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 paper/data/example_gen.v

(limited to 'paper/data/example_gen.v')

diff --git a/paper/data/example_gen.v b/paper/data/example_gen.v
new file mode 100644
index 0000000..21c78a0
--- /dev/null
+++ b/paper/data/example_gen.v
@@ -0,0 +1,56 @@
+module top #(parameter param0 = 5'h9e23848124)
+(y, clk, wire0, wire1, wire2, wire3);
+  // *** Declarations ***
+  output wire [(5'h31):(1'h0)] y;
+  input wire [(1'h0):(1'h0)] clk;
+  input wire [(3'h6):(1'h0)] wire0;
+  input wire [(4'ha):(1'h0)] wire1;
+  input wire signed [(4'ha):(1'h0)] wire2;
+  input wire [(4'hb):(1'h0)] wire3;
+  reg [(3'h2):(1'h0)] reg20 = (1'h0);
+  reg [(3'h5):(1'h0)] reg19 = (1'h0);
+  reg [(3'h4):(1'h0)] reg18 = (1'h0);
+  reg [(2'h2):(1'h0)] reg17 = (1'h0);
+  reg [(4'ha):(1'h0)] reg16 = (1'h0);
+  reg signed [(4'h9):(1'h0)] reg15 = (1'h0);
+  wire [(3'h6):(1'h0)] wire5;
+  wire [(2'h3):(1'h0)] wire4;
+  // *** Assign output ***
+  assign y =
+    {reg20,reg19,reg18,reg17,reg16,reg15,wire5,wire4};
+  // *** Random module items ***
+  assign wire4 = (((~wire1) ? ((((15'h9ecc51592fdeb04)
+    ? reg17[(5'h2):(2'h2)] : (reg18 ? wire2 : wire0))
+    ? $unsigned(((-2'ha73a956341f45c0) << reg18)) :
+    wire1[(4'ha):(3'h7)]) - reg18) :
+    reg15[(4'h9):(3'h7)]) >>> $unsigned($signed((
+    reg16[(4'ha):(3'h7)] ? ((wire1 && reg16) &&
+    {reg15, reg15, wire3}) : (reg18 ? (~&wire3) :
+    (-39'ha7a1419cd4ea34a))))));
+  assign wire5 = $signed(((wire2 ? (
+    (-8'h5e411249da4f335) ? (4'hb2fa97daeae9ff) :
+    wire1) : (wire4 ? wire2 : wire1)) ?
+    $signed(wire3) : ({(7'hbac46141008d14)} >>>
+    (&wire0))));
+  always @(posedge clk) begin
+    for (reg15 = (1'h0); (reg15 < (2'h2)); reg15 =
+        (reg15 + (1'h1))) begin
+      if (((wire3 == (~(reg16 + wire1))) >=
+          {$signed(wire0[(2'h2):(1'h0)])}))
+        reg16 <=  ($unsigned($unsigned(wire1)) <
+          wire3[(1'h1):(1'h1)]);
+      else reg16 <= $unsigned(reg17[(2'h2):(2'h0)]);
+      reg17 <=  wire3[(1'h0):(1'h0)];
+    end
+    reg18 <= $signed(({wire0} ~^ wire3));
+  end
+  always @(posedge clk) begin
+    if (wire3[(4'h9):(3'h6)])
+      reg19 = $signed($unsigned(wire1)) <<
+        $unsigned({wire1});
+    reg20 <=  ({({(~|wire3), $unsigned(reg19)} ?
+      reg16 : reg15[(2'h2):(1'h1)]),
+      (~&((wire0 ? wire3 : reg17) ~^ reg18))}
+      || ((~&(wire3[(4'hb):(4'h9)] ? wire4 : (+wire5)))));
+  end
+endmodule
-- 
cgit