From f9ca386bda2fe89287b9bb65d3d28e0c150d8984 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 7 Oct 2021 13:43:16 +0100 Subject: Add initial files --- presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys/top.v | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys/top.v (limited to 'presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys') diff --git a/presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys/top.v b/presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys/top.v new file mode 100644 index 0000000..0700c08 --- /dev/null +++ b/presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys/top.v @@ -0,0 +1,8 @@ +module top (y_1, y_2, clk, wire0, wire1, wire2, wire3); + top_gen top_gen (.y(y_1), .clk(clk), .wire0(wire0), .wire1(wire1), .wire2(wire2), .wire3(wire3)); + top_syn top_syn (.y(y_2), .clk(clk), .wire0(wire0), .wire1(wire1), .wire2(wire2), .wire3(wire3)); + always + @(posedge clk) begin + assert ((y_1 == y_2)); + end +endmodule -- cgit