From f9ca386bda2fe89287b9bb65d3d28e0c150d8984 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Thu, 7 Oct 2021 13:43:16 +0100 Subject: Add initial files --- .../ExampleRun/output2/fuzz_1/reduce_sim_yosys.v | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 presentation/ExampleRun/output2/fuzz_1/reduce_sim_yosys.v (limited to 'presentation/ExampleRun/output2/fuzz_1/reduce_sim_yosys.v') diff --git a/presentation/ExampleRun/output2/fuzz_1/reduce_sim_yosys.v b/presentation/ExampleRun/output2/fuzz_1/reduce_sim_yosys.v new file mode 100644 index 0000000..ea01016 --- /dev/null +++ b/presentation/ExampleRun/output2/fuzz_1/reduce_sim_yosys.v @@ -0,0 +1,27 @@ +// -*- mode: verilog -*- +module top (y, clk, wire0, wire1, wire2, wire3); + output wire [(32'hb7):(32'h0)] y ; + input wire [(1'h0):(1'h0)] clk ; + input wire signed [(5'h11):(1'h0)] wire0 ; + input wire signed [(4'ha):(1'h0)] wire1 ; + input wire [(4'hd):(1'h0)] wire2 ; + input wire [(4'h8):(1'h0)] wire3 ; + reg [(2'h3):(1'h0)] reg5 = (1'h0) ; + reg [(5'h14):(1'h0)] reg6 = (1'h0) ; + reg signed [(5'h12):(1'h0)] reg7 = (1'h0) ; + reg [(4'hd):(1'h0)] reg8 = (1'h0) ; + assign y = {reg5, reg6, reg7, reg8} ; + always + @(posedge clk) begin + reg5 <= (1'h0); + reg6 <= wire1; + reg7 <= ((~|((wire0 & {wire3, + (1'h0)}) | $unsigned(((1'h0) != (8'h9d))))) <<< ((wire1[(2'h2):(2'h2)] + ((~(8'ha7)) ? + wire3 : $signed(wire1))) ? + $unsigned(((^wire0) + $unsigned(wire3))) : (((reg5 * wire3) ? + wire1 : $unsigned(reg6)) ? + {{(1'h0), wire2}} : (reg5[(1'h0):(1'h0)] ? + $signed((1'h0)) : (~wire3))))); + reg8 <= (~^$unsigned(reg6)); + end +endmodule \ No newline at end of file -- cgit