module top_1(y, clk, wire1);
   input clk;
   wire [1:0] reg4;
   input wire1;
   output [1:0] y;
   reg reg4_reg[0]  = 1'hx;
   always @(posedge clk)
     reg4_reg[0]  <= wire1;
   assign reg4[0] = reg4_reg[0] ;
   assign reg4[1] = reg4[0];
   assign y = { reg4[0], reg4[0] };
endmodule