module top (y_1, y_2, clk, wire0, wire1, wire2, wire3);
  top_gen top_gen (.y(y_1), .clk(clk), .wire0(wire0), .wire1(wire1), .wire2(wire2), .wire3(wire3));
  top_syn top_syn (.y(y_2), .clk(clk), .wire0(wire0), .wire1(wire1), .wire2(wire2), .wire3(wire3));
  always
    @(posedge clk) begin
      assert ((y_1 == y_2));
    end
endmodule