From 946ce4e23e55227fcf583c56da676f59ea736109 Mon Sep 17 00:00:00 2001 From: John Wickerson Date: Wed, 24 Feb 2021 10:48:29 +0000 Subject: Update on Overleaf. --- main.tex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/main.tex b/main.tex index dbdcc44..2089652 100644 --- a/main.tex +++ b/main.tex @@ -185,7 +185,7 @@ \renewcommand{\epigraphsize}{\normalsize} \renewcommand{\epigraphflush}{center} \renewcommand{\epigraphrule}{0pt} -\epigraph{\textit{High-level synthesis research and development is inherently prone to introducing bugs or regressions in the final circuit functionality.}}{--- Andrew Canis~\cite{canis15_legup}} +\epigraph{\textit{High-level synthesis research and development is inherently prone to introducing bugs or regressions in the final circuit functionality.}}{--- Andrew Canis \JW{Co-founder of LegUp Computing}~\cite{canis15_legup}} %\JW{Nice quote; I'd be tempted to tinker with whether it can be formatted a bit more elegantly, like at https://style.mla.org/styling-epigraphs/} Research in high-level synthesis (HLS) often concentrates on performance, trying to achieve the lowest area with the shortest run-time. What is often overlooked is ensuring that the high-level synthesis tool is indeed correct, which means that it outputs a correct hardware design. Instead, the design is often meticulously tested, often using the higher level design as a model. As these tests are performed on the hardware design directly, they have to be run on a simulator, which takes much longer than if the original C was tested. Any formal properties obtained from the C code would also have to be checked again in the resulting design, to ensure that these hold there as well, as the synthesis tool may have translated the input incorrectly. -- cgit