From 4355f514ce2f7de3d75fd02e8119d1c193a7b497 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Tue, 23 Feb 2021 11:17:25 +0000
Subject: More work

---
 references.bib | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)

(limited to 'references.bib')

diff --git a/references.bib b/references.bib
index 24b1f75..242532b 100644
--- a/references.bib
+++ b/references.bib
@@ -87,3 +87,92 @@
 	numpages = 9,
 	publisher = {ACM}
 }
+
+@inproceedings{kim04_autom_fsmd,
+	author = { {Youngsik Kim} and S. {Kopuri} and N. {Mansouri}},
+	title = {Automated formal verification of scheduling process using finite state machines with datapath (FSMD)},
+	tags = {hls, verification},
+	booktitle = {International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720)},
+	year = 2004,
+	pages = {110-115},
+	doi = {10.1109/ISQED.2004.1283659},
+	url = {https://doi.org/10.1109/ISQED.2004.1283659},
+	ISSN = {null},
+	month = {March}
+}
+
+@inproceedings{karfa06_formal_verif_method_sched_high_synth,
+	author = {Karfa, C and Mandal, C and Sarkar, D and Pentakota, S R. and
+                  Reade, Chris},
+	title = {A Formal Verification Method of Scheduling in High-level Synthesis},
+	tags = {hls},
+	booktitle = {Proceedings of the 7th International Symposium on Quality Electronic Design},
+	year = 2006,
+	pages = {71--78},
+	doi = {10.1109/ISQED.2006.10},
+	url = {https://doi.org/10.1109/ISQED.2006.10},
+	acmid = 1126731,
+	address = {Washington, DC, USA},
+	isbn = {0-7695-2523-7},
+	numpages = 8,
+	publisher = {IEEE Computer Society},
+	series = {ISQED '06}
+}
+
+@article{chouksey20_verif_sched_condit_behav_high_level_synth,
+	author = {R. {Chouksey} and C. {Karfa}},
+	title = {Verification of Scheduling of Conditional Behaviors in High-Level Synthesis},
+	journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
+	volume = {},
+	number = {},
+	pages = {1-14},
+	year = {2020},
+	doi = {10.1109/TVLSI.2020.2978242},
+	url = {https://doi.org/10.1109/TVLSI.2020.2978242},
+	ISSN = {1557-9999},
+	month = {}
+}
+
+@article{banerjee14_verif_code_motion_techn_using_value_propag,
+	author = {K. {Banerjee} and C. {Karfa} and D. {Sarkar} and C. {Mandal}},
+	title = {Verification of Code Motion Techniques Using Value Propagation},
+	tags = {hls, verification},
+	journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+	volume = 33,
+	number = 8,
+	pages = {1180-1193},
+	year = 2014,
+	doi = {10.1109/TCAD.2014.2314392},
+	url = {https://doi.org/10.1109/TCAD.2014.2314392},
+	ISSN = {1937-4151},
+	keywords = {translation validation, compiler optimisation, verification, high-level synthesis},
+	month = {Aug}
+}
+
+@article{chouksey19_trans_valid_code_motion_trans_invol_loops,
+	author = {R. {Chouksey} and C. {Karfa} and P. {Bhaduri}},
+	title = {Translation Validation of Code Motion Transformations Involving Loops},
+	tags = {hls, verification},
+	journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
+	volume = 38,
+	number = 7,
+	pages = {1378-1382},
+	year = 2019,
+	doi = {10.1109/TCAD.2018.2846654},
+	url = {https://doi.org/10.1109/TCAD.2018.2846654},
+	ISSN = {1937-4151},
+	keywords = {translation validation, verification, compiler optimisation, high-level synthesis},
+	month = {July}
+}
+
+@inproceedings{pnueli98_trans,
+	author = "Pnueli, A.  and Siegel, M.  and Singerman, E.",
+	title = "Translation validation",
+	booktitle = "Tools and Algorithms for the Construction and Analysis of Systems",
+	year = 1998,
+	pages = "151--166",
+	address = "Berlin, Heidelberg",
+	editor = "Steffen, Bernhard",
+	isbn = "978-3-540-69753-4",
+	publisher = "Springer Berlin Heidelberg"
+}
-- 
cgit