From 004bd0b86c72ccf7a1e24526c7b5184cd8486b7e Mon Sep 17 00:00:00 2001
From: John Wickerson <j.wickerson@imperial.ac.uk>
Date: Fri, 16 Apr 2021 09:26:31 +0000
Subject: Update on Overleaf.

---
 algorithm.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/algorithm.tex b/algorithm.tex
index 855208d..c214392 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -150,7 +150,7 @@ module main(reset, clk, finish, return_val);
          endcase
 endmodule
 \end{minted}
-\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM (lines 9--15), \JW{Sorry about the absolu} the data-path (lines 16--32) and the control logic (lines 33--42).}\label{fig:accumulator_v}
+\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM (lines 9--15), \JW{Sorry about the magic numbers here} the data-path (lines 16--32) and the control logic (lines 33--42).}\label{fig:accumulator_v}
 \end{subfigure}
   \caption{Translating a simple program from C to Verilog.}\label{fig:accumulator_c_rtl}
 \end{figure}
-- 
cgit