From 11a01605225c1cbc9ff52277350972175cf37713 Mon Sep 17 00:00:00 2001 From: Yann Herklotz Date: Tue, 9 Jun 2020 13:18:18 +0100 Subject: Add comment --- main.tex | 1 + 1 file changed, 1 insertion(+) diff --git a/main.tex b/main.tex index b39de48..a0bc2b0 100644 --- a/main.tex +++ b/main.tex @@ -213,6 +213,7 @@ CoqUp is open source and is hosted on Github\footnote{https://github.com/ymherkl \YH{Amazing, thank you, yes it seems like Kundu \textit{et al.} have quite a few papers on formal verification of HLS algorithms using translation validation, as well as~\citet{karfa06_formal_verif_method_sched_high_synth}, all using the SPARK~\cite{gupta03_spark} synthesis tool. And yes thank you, will definitely cite that paper. There seem to be similar early proofs of high-level synthesis like \citet{hwang91_formal_approac_to_sched_probl} or \citet{grass94_high}. There are also the Occam papers that I need to mention too, like \citet{page91_compil_occam}, \citet{jifeng93_towar}, \citet{perna11_correc_hardw_synth} and \citet{perna12_mechan_wire_wise_verif_handel_c_synth}.} \JW{Well it's a good job there's no page limit on bibliographies these days then! I'll keep an eye out for more papers we could cite when I get a free moment. (No need to cite \emph{everything} of course.)} +\YH{Yes that's true, there are too many to cite! And great thank you, that would help a lot, I have quite a few papers I still want to cite, but have to think about where they will fit in.} \section{Verilog Semantics} -- cgit