From 5a9c5a4c6aed0d05396b2c04b3148377ee38d2b1 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Sun, 3 Oct 2021 17:55:40 +0100
Subject: Update presentation and add new images

---
 main.pdf                              | Bin 0 -> 703187 bytes
 presentation/assets/database-cpu.pdf  | Bin 0 -> 52727 bytes
 presentation/assets/database-fpga.pdf | Bin 0 -> 55641 bytes
 presentation/presentation.org         |  66 +++++++++++++++++++++++++---------
 presentation/presentation.pdf         | Bin 2300589 -> 2410099 bytes
 5 files changed, 50 insertions(+), 16 deletions(-)
 create mode 100644 main.pdf
 create mode 100644 presentation/assets/database-cpu.pdf
 create mode 100644 presentation/assets/database-fpga.pdf

diff --git a/main.pdf b/main.pdf
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index 0000000..7fc27d4
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diff --git a/presentation/assets/database-cpu.pdf b/presentation/assets/database-cpu.pdf
new file mode 100644
index 0000000..1a4c4ef
Binary files /dev/null and b/presentation/assets/database-cpu.pdf differ
diff --git a/presentation/assets/database-fpga.pdf b/presentation/assets/database-fpga.pdf
new file mode 100644
index 0000000..ea5221b
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diff --git a/presentation/presentation.org b/presentation/presentation.org
index a12368a..e545568 100644
--- a/presentation/presentation.org
+++ b/presentation/presentation.org
@@ -6,20 +6,54 @@
 
 ** The Need to Design Hardware Accelerators
 
-Field-programmable gate arrays (FPGAs) becoming more popular as flexible hardware acceleration.
+Hardware accelerators are needed more and more industries.
 
-Compared to microcontrollers:
+*** Column 1
+:PROPERTIES:
+:BEAMER_ENV: column
+:BEAMER_COL: 0.5
+:END:
 
-- Can greatly *reduce latency*.
-- Lower *power*.
-- *Higher performance*.
+#+attr_beamer: :overlay <+->
+- Using a *CPU* everywhere not always the best choice.
+- *Field-Programmable Gate Arrays (FPGA)* provide a good alternative.
+- FPGAs act as *reprogrammable hardware*, therefore can be made application specific.
 
-But:
+*** Column 2
+:PROPERTIES:
+:BEAMER_ENV: column
+:BEAMER_COL: 0.5
+:END:
 
-- Needs knowledge about hardware design.
-- *Less flexible*.
+**** Minipage
+:PROPERTIES:
+:BEAMER_ENV: minipage
+:BEAMER_OPT: 5cm
+:END:
 
-** FPGA Layout
+#+beamer: \vspace{2em}
+
+***** Only 1
+:PROPERTIES:
+:BEAMER_ENV: onlyenvNH
+:BEAMER_ACT: 1
+:END:
+
+#+begin_export latex
+\includegraphics[width=6cm]{assets/database-cpu.pdf}
+#+end_export
+
+***** Only 2
+:PROPERTIES:
+:BEAMER_ENV: onlyenvNH
+:BEAMER_ACT: 2-
+:END:
+
+#+begin_export latex
+\includegraphics[width=6cm]{assets/database-fpga.pdf}
+#+end_export
+
+** Where does the flexibility of FPGAs come from?
 
 #+attr_beamer: :overlay <+->
 - FPGA's are programmable circuits with two main components.
@@ -370,7 +404,7 @@ main() {
 
 ** Example: HTL Overview
 
-The representation of the *finite state-machine with datapath (FSMD)* is abstract and called **HTL**.
+The representation of the *finite state-machine with datapath* is abstract and called **HTL**.
 
 *** Datapath and control logic :B_blockNH:
 :PROPERTIES:
@@ -401,7 +435,7 @@ Record module: Type := mkmodule {
 
 ** Example: Translation (3AC $\rightarrow$ HTL)
 
-Translation from *control-flow graph (CFG)* into a *finite state-machine with datapath (FSMD)*.
+Translation from *control-flow graph* into a *finite state-machine with datapath*.
 
 #+beamer: \pause
 #+beamer: \vspace{1em}
@@ -415,13 +449,13 @@ Translation from *control-flow graph (CFG)* into a *finite state-machine with da
 
 #+beamer: \vspace{1em}
 
-*** Minipage :B_minipage:
+*** Minipage :B_minipage:noexport:
 :PROPERTIES:
 :BEAMER_env: minipage
 :BEAMER_OPT: 5cm
 :END:
 
-**** Only 1 :B_onlyenvNH:
+**** Only 1 :B_onlyenvNH:noexport:
 :PROPERTIES:
 :BEAMER_env: onlyenvNH
 :BEAMER_ACT: 3
@@ -429,7 +463,7 @@ Translation from *control-flow graph (CFG)* into a *finite state-machine with da
 
 ~x3 = x3 + x5 + 0~ $\quad\longrightarrow\quad$ src_verilog[:exports code]{reg_3 <= {reg_3 + {reg_5 + 32'd0}}}
 
-**** Only 2 :B_onlyenvNH:
+**** Only 2 :B_onlyenvNH:noexport:
 :PROPERTIES:
 :BEAMER_env: onlyenvNH
 :BEAMER_ACT: 5-6
@@ -974,7 +1008,7 @@ Prove the simulation diagram correct:
 
 * Results
 
-** With Division approximately 27$\times$ slower
+** The bad news: with division approximately 27$\times$ slower
 
 #+begin_export latex
 \pgfplotstableread[col sep=comma]{../results/rel-time-div.csv}{\divtimingtable}
@@ -1039,7 +1073,7 @@ Prove the simulation diagram correct:
 \end{tikzpicture}
 #+end_export
 
-** Without Division about 2$\times$ slower
+** The better news: without division about 2$\times$ slower
 
 #+begin_export latex
 \pgfplotstableread[col sep=comma]{../results/rel-time-nodiv.csv}{\nodivtimingtable}
diff --git a/presentation/presentation.pdf b/presentation/presentation.pdf
index b13e1cb..acef371 100644
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-- 
cgit