From 06ca7a1b9126e27d6e3c34dbd3637f167be1efc8 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 7 Apr 2021 19:46:27 +0100
Subject: Fix some formatting

---
 algorithm.tex | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'algorithm.tex')

diff --git a/algorithm.tex b/algorithm.tex
index fbf8df1..6ab06c4 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -72,7 +72,7 @@ It has an unlimited number of pseudo-registers, and is represented as a control
 
 \begin{figure}
   \centering
-  \begin{subfigure}[b]{0.49\linewidth}
+  \begin{subfigure}[b]{0.24\linewidth}
 \begin{minted}{c}
 int main() {
   int x[3] = {1, 2, 3};
@@ -85,8 +85,8 @@ int main() {
 }
 \end{minted}
     \caption{Input C code.}\label{fig:accumulator_c}
-  \end{subfigure}\hspace*{-4mm}
-  \begin{subfigure}[b]{0.49\linewidth}
+  \end{subfigure}
+  \begin{subfigure}[b]{0.24\linewidth}
 \begin{minted}[fontsize=\footnotesize]{c}
 main() {
  15:  x8 = 1
@@ -107,8 +107,8 @@ main() {
 }
 \end{minted}
     \caption{3AC produced by \compcert{}.}\label{fig:accumulator_rtl}
-  \end{subfigure}\hfill%
-\begin{subfigure}[b]{1\linewidth}
+  \end{subfigure}
+\begin{subfigure}[b]{0.48\linewidth}
 \vspace{1em}
 \begin{minted}[fontsize=\tiny]{verilog}
 module main(reset, clk, finish, return_val);
-- 
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