From 14b7a9d9e7c09b34efd050ed52400cb95a139f1d Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Wed, 14 Apr 2021 12:15:52 +0100
Subject: Add comments

---
 algorithm.tex | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'algorithm.tex')

diff --git a/algorithm.tex b/algorithm.tex
index 930e3ca..14d1496 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -113,11 +113,13 @@ module main(reset, clk, finish, return_val);
   reg [0:0] en = 0, u_en = 0;
   reg [31:0] state = 0, reg_2 = 0, reg_4 = 0, d_out = 0, reg_1 = 0;
   reg [31:0] stack [1:0];
+  // RAM Template
   always @(negedge clk)
     if ({u_en != en}) begin
       if (wr_en) stack[addr] <= d_in; else d_out <= stack[addr];
       en <= u_en;
     end
+  // Data-path
   always @(posedge clk)
     case (state)
       32'd11: reg_2 <= d_out;
@@ -134,6 +136,7 @@ module main(reset, clk, finish, return_val);
       32'd1: begin finish = 32'd1; return_val = reg_2; end
       default: ;
     endcase
+  // Control logic
   always @(posedge clk)
     if ({reset == 32'd1}) state <= 32'd8;
     else case (state)
@@ -145,7 +148,7 @@ module main(reset, clk, finish, return_val);
          endcase
 endmodule
 \end{minted}
-\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM, the data-path and finally the control-logic.}\label{fig:accumulator_v}
+\caption{Verilog produced by \vericert{}. It demonstrates the instantiation of the RAM, the data-path and finally the control logic.}\label{fig:accumulator_v}
 \end{subfigure}
   \caption{Translating a simple program from C to Verilog.}\label{fig:accumulator_c_rtl}
 \end{figure}
-- 
cgit