From 8f933de85b235141b719f10b0f7c44f4275444df Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Mon, 13 Sep 2021 09:30:33 +0100
Subject: Fix typo

---
 algorithm.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'algorithm.tex')

diff --git a/algorithm.tex b/algorithm.tex
index 5138915..c1ccd10 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -362,7 +362,7 @@ Compared to plain Verilog, HTL is simpler to manipulate and analyse, thereby mak
 \end{scope}
 \end{tikzpicture}
   \Description{Diagram displaying the data-path and its internal modules, as well as the control logic and its state machine.}
-  \caption{The FSMD for the example shown in Fig.~\ref{fig:accumulator_c_rtl}, split into a data-path and control logic for the next state calculation.  The Update block takes the current state, current values of all registers and at most one value stored in the RAM, and calculates a new value that can either be stored back in the  or in a register.}\label{fig:accumulator_diagram}
+  \caption{The FSMD for the example shown in Fig.~\ref{fig:accumulator_c_rtl}, split into a data-path and control logic for the next state calculation.  The Update block takes the current state, current values of all registers and at most one value stored in the RAM, and calculates a new value that can either be stored back in the RAM or in a register.}\label{fig:accumulator_diagram}
 \end{figure*}
 
 %\JP{Does it? Verilog has neither physical registers nor RAMs, just language constructs which the synthesiser might implement with registers and RAMs. We should be clear whether we're talking about the HDL representation, or the synthesised result: in our case these can be very different since we don't target any specific architectural features of an FPGA fabric of ASIC process.}
-- 
cgit 

