From a61f0a5b3a4664f2e1f42e788cc195a7d56ade28 Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Fri, 10 Sep 2021 15:46:02 +0100
Subject: Make the diagram larger and add copyright

---
 algorithm.tex | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'algorithm.tex')

diff --git a/algorithm.tex b/algorithm.tex
index a4941d5..0182d70 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -35,7 +35,7 @@ The .NET framework has been used as a basis for other HLS tools, such as Kiwi~\c
     continuation/.style={},
     linecount/.style={rounded corners=3pt,dashed}]
     \fill[compcert,rounded corners=3pt] (-1,-0.5) rectangle (9.9,2);
-    \fill[formalhls,rounded corners=3pt] (-1,-1) rectangle (9.9,-2);
+    \fill[formalhls,rounded corners=3pt] (-1,-1) rectangle (9.9,-2.4);
     %\draw[linecount] (-0.95,-0.45) rectangle (3.6,1);
     %\draw[linecount] (4,-0.45) rectangle (7.5,1);
     \node[language] at (-0.3,0) (clight) {Clight};
@@ -54,7 +54,7 @@ The .NET framework has been used as a basis for other HLS tools, such as Kiwi~\c
     %%\node[anchor=west] at (-0.9,0.7) {\small $\sim$ 27 kloc};
     %%\node[anchor=west] at (4.1,0.7) {\small $\sim$ 46 kloc};
     %%\node[anchor=west] at (2,-1.5) {\small $\sim$ 17 kloc};
-    \node[align=center] at (3.5,-2.4) {\footnotesize RAM\\[-0.5em]\footnotesize insertion};
+    \node[align=center] at (3.2,-2) {\footnotesize RAM\\[-0.5em]\footnotesize insertion};
     \draw[->,thick] (clight) -- (conta);
     \draw[->,thick] (conta) -- (cminor);
     \draw[->,thick] (cminor) -- (rtl);
@@ -67,7 +67,7 @@ The .NET framework has been used as a basis for other HLS tools, such as Kiwi~\c
     \draw[->,thick] (htl) -- (verilog);
     \draw[->,thick] (htl.west) to [out=180,in=150] (4,-2.2) to [out=330,in=270] (htl.south);
   \end{tikzpicture}%}
-  \caption{\vericert{} as a Verilog back end to \compcert{}. \JW{The placement of the `RAM insertion' label suggests that it's not part of Vericert. Maybe move it inside the orange rectangle?}}%
+  \caption{\vericert{} as a Verilog back end to \compcert{}.}%
   \label{fig:rtlbranch}
 \end{figure}
 
-- 
cgit 

