From a95b15a7b3857879c8ef01d32137fedb73575581 Mon Sep 17 00:00:00 2001
From: John Wickerson <j.wickerson@imperial.ac.uk>
Date: Fri, 16 Apr 2021 09:37:15 +0000
Subject: Update on Overleaf.

---
 algorithm.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'algorithm.tex')

diff --git a/algorithm.tex b/algorithm.tex
index 32c14ba..2a903da 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -311,7 +311,7 @@ Finally, the \texttt{mulhs} and \texttt{mulhu} instructions, which fetch the upp
 However, 64-bit number representations are currently not supported in the generated hardware, so this operation cannot currently be performed.  These instructions are only generated to optimise divides \JW{divisions?} by a constant \JWcouldcut{number} that is not a power of two, so turning off constant propagation will allow these programs to pass without error.
 
 \subsubsection{RAM insertion}
-\JW{I thought this was going in to}
+\JW{I thought this was going in the `}
 This pass goes from HTL \JWcouldcut{back} to HTL and extracts all the direct accesses to the Verilog array implementing memory and replaces them by signals which access the memory in a separate always-block.  This ensures that the synthesis tool correctly identifies the array as being a RAM, so that it is not implemented by logic directly.  The translation is performed by going through all the instructions and replacing each load and store expression one after another.  Stores can simply be replaced by the necessary wires directly, however, loads using the RAM block take two clock cycles instead of a direct load from an array which only takes one clock cycles.  This pass therefore creates a extra state which is inserted after each load.
 
 \subsubsection{Translating HTL to Verilog}
-- 
cgit 

