From f71e5db19dd21b9354d64ad555b9e34c8b7d487e Mon Sep 17 00:00:00 2001
From: Yann Herklotz <git@yannherklotz.com>
Date: Fri, 10 Sep 2021 17:32:32 +0100
Subject: Replace x by tmp

---
 algorithm.tex | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'algorithm.tex')

diff --git a/algorithm.tex b/algorithm.tex
index 3d65607..f4e276c 100644
--- a/algorithm.tex
+++ b/algorithm.tex
@@ -96,11 +96,11 @@ Verilog behaves quite differently to standard software programming languages due
 \begin{minted}[linenos,xleftmargin=20pt,fontsize=\footnotesize]{verilog}
 module main(input rst, input y, input clk,
             output reg z);
-  reg x, state;
+  reg tmp, state;
   always @(posedge clk)
     case (state)
-      1'b0: x <= y;
-      1'b1: begin x <= 1'b0; z <= x; end
+      1'b0: tmp <= y;
+      1'b1: begin tmp <= 1'b0; z <= tmp; end
     endcase
   always @(posedge clk)
     if (rst) state <= 1'b0;
@@ -139,7 +139,7 @@ endmodule
 
 
 A simple state machine can be implemented as shown in Fig.~\ref{fig:tutorial:state_machine}.
-At every positive edge of the clock (\texttt{clk}), both of the always-blocks will trigger simultaneously.  The first always-block controls the values in the register \texttt{x} and the output \texttt{z}, while the second always-block controls the next state the state machine should go to.  When the \texttt{state} is 0, \texttt{x} will be assigned to the input \texttt{y} using nonblocking assignment, denoted by \texttt{<=}.  Nonblocking assignment assigns registers in parallel at the end of the clock cycle, rather than sequentially throughout the always-block. In the second always-block, the input \texttt{y} will be checked, and if it's high it will move on to the next state, otherwise it will stay in the current state.  When \texttt{state} is 1, the first always-block will reset the value of \texttt{x} and then set \texttt{z} to the original value of \texttt{x}, since nonblocking assignment does not change its value until the end of the clock cycle.  Finally, the last always-block will set the state to be 0 again.
+At every positive edge of the clock (\texttt{clk}), both of the always-blocks will trigger simultaneously.  The first always-block controls the values in the register \texttt{x} and the output \texttt{z}, while the second always-block controls the next state the state machine should go to.  When the \texttt{state} is 0, \texttt{tmp} will be assigned to the input \texttt{y} using nonblocking assignment, denoted by \texttt{<=}.  Nonblocking assignment assigns registers in parallel at the end of the clock cycle, rather than sequentially throughout the always-block. In the second always-block, the input \texttt{y} will be checked, and if it's high it will move on to the next state, otherwise it will stay in the current state.  When \texttt{state} is 1, the first always-block will reset the value of \texttt{tmp} and then set \texttt{z} to the original value of \texttt{tmp}, since nonblocking assignment does not change its value until the end of the clock cycle.  Finally, the last always-block will set the state to be 0 again.
 
 \begin{figure}
   \centering
-- 
cgit 

